AD9786 Datasheet, PDF (8/60 Pages) Analog Devices – 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2×/4×/8× Interpolation and Signal Processing

AD9786
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
CLKVDD 1
DNG 2
CLKVDD 3
CLKGND 4
CLK+ 5
CLK– 6
CLKGND 7
DGND 8
DVDD 9
P1B15 10
P1B14 11
P1B13 12
P1B12 13
P1B11 14
P1B10 15
DGND 16
DVDD 17
P1B9 18
P1B8 19
P1B7 20
PIN 1
IDENTIFIER
AD9786
TOP VIEW
(Not to Scale)
60 FSADJ
59 REFIO
58 RESET
57 CSB
56 SCLK
55 SDIO
54 SDO
53 DGND
52 DVDD
51 P2B0
50 P2B1
49 P2B2
48 P2B3
47 P2B4
46 P2B5
45 DGND
44 DVDD
43 P2B6
42 P2B7
41 P2B8
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
DNC = DO NOT CONNECT
Figure 2. Pin Configuration
CLOCK
Table 5. Clock Pin Function Descriptions
Pin
No. Name
Direction Description
5, 6 CLK+, CLK–
I
Differential Clock Input.
2
DNC
Do Not Connect.
31 DATACLK
I/O
DCLKEXT
02h[3] Mode
0
Pin configured for input of channel data rate or synchronizer clock.
Internal clock synchronizer may be turned on or off with DCLKCRC
(02h[2]).
1
Pin configured for output of channel data rate or synchronizer
clock.
1, 3 CLKVDD
Clock Domain 2.5 V.
4, 7 CLKGND
Clock Domain 0 V.
Rev. 0 | Page 8 of 60