AD9786 Datasheet, PDF (1/60 Pages) Analog Devices – 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2×/4×/8× Interpolation and Signal Processing

16-Bit, 200 MSPS/500 MSPS TxDAC+^® with
2×/4×/8× Interpolation and Signal Processing
AD9786
FEATURES
16-bit resolution, 200 MSPS input data rate
IMD 90 dBc @10 MHz
Noise spectral density (NSD) −164 dBm/Hz @ 10 MHz
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = ±0.3 LSB
INL = ±0.6 LSB
Selectable 2×/4×/8× interpolation filters
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single or dual channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface
3.3 V compatible digital interface
On-chip 1.2 V reference
80-lead thermally enhanced TQFP package
APPLICATIONS
Base stations: Multicarrier WCDMA, GSM/EDGE, TD-SCDMA,
IS136, TETRA
Instrumentation: RF Signal Generators, Arbitrary Waveform
Generators
HDTV Transmitters
Broadband Wireless Systems
Digital Radio Links
Satellite Systems
PRODUCT DESCRIPTION
The AD9786 is a 16-bit, high speed, CMOS DAC with 2×/4×/8×
interpolation and signal processing features tuned for com-
munications applications. It offers state-of-the-art distortion
and noise performance. The AD9786 was developed to meet the
demanding performance requirements of multicarrier and third
generation base stations. The selectable interpolation filters
simplify interfacing to a variety of input data rates while also
taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.
The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single-ended or
differential mode. Internal dividers generate the required data
rate interface clocks.
The AD9786 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9786 is
manufactured on an advanced low cost 0.25 µm CMOS process.
FUNCTIONAL BLOCK DIAGRAM
P1B[15:0]
P2B[15:0]
DATACLK
LATCH
2×
×1
LATCH
2×
2×
2×
Q
0
90
f_DAC/2
f_DAC/4
f_DAC/8
0
90
0
90
Q
2×
2×
∆t
ZERO
STUFF
16-BIT DAC
HILBERT
FSADJ
REFIO
I_OUTA
I_OUTB
SDIO
SDO
CSB
SCLK
RESET
CLK+
CLK–
CLOCK DISTRIBUTION AND CONTROL
Figure 1.
Rev. 0
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