AD9559BCPZ Datasheet, PDF (9/120 Pages) Analog Devices – Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

Data Sheet
AD9559
Parameter
Min
Typ
Rise/Fall Time (20% to 80%)¹
1.8 V Mode
1.5
3.3 V Strong Mode
0.4
3.3 V Weak Mode
8
Duty Cycle
1.8 V Mode
50
3.3 V Strong Mode
47
51
3.3 V Weak Mode
51
Output Voltage High (VOH)
VDD3 = 3.3 V, IOH = 10 mA
VDD3 − 0.3
VDD3 = 3.3 V, IOH = 1 mA
VDD3 − 0.1
VDD3 = 1.8 V, IOH = 1 mA
Output Voltage Low (VOL)
VDD − 0.2
VDD3 = 3.3 V, IOL = 10 mA
VDD3 = 3.3 V, IOL = 1 mA
VDD3 = 1.8 V, IOL = 1 mA
OUTPUT TIMING SKEW
Between OUT0A, OUT0A and OUT0B, OUT0B
116
or OUT1A, OUT1A and OUT1B, OUT1B
Additional Delay on One Driver by
Changing Its Logic Type
HSTL to LVDS
0
+15
HSTL to 1.8 V CMOS
−5
0
OUT0B, OUT0B HSTL to OUT0B, OUT0B
3.3 V CMOS, Strong Mode
OUT1B, OUT1B HSTL to OUT1B, OUT1B
3.3 V CMOS, Strong Mode
−765
−765
1 _{The listed values are for the slower edge (rising or falling).}
−280
−280
Max
3
0.6
56
0.3
0.1
0.1
265
+35
+5
+250
+250
Unit Test Conditions/Comments
ns
10 pF load
ns
10 pF load
ns
10 pF load
%
10 pF load
%
10 pF load
%
10 pF load
Output driver static; strong drive strength
V
V
V
Output driver static; strong drive strength
V
V
V
10 pF load
ps
HSTL mode on both drivers; rising edge only;
any divide value
ps
Positive value indicates that the LVDS edge is
delayed relative to HSTL
ps
Positive value indicates that the CMOS edge is
delayed relative to HSTL
ns
The CMOS edge is delayed relative to HSTL
ns
The CMOS edge is delayed relative to HSTL
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