AD9559BCPZ Datasheet, PDF (24/120 Pages) Analog Devices – Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

AD9559
80
1.8V CMOS
3.3V CMOS WEAK
70
3.3V CMOS STRONG
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180 200
FREQUENCY (MHz)
Figure 21. Power Consumption vs. Frequency for Two CMOS Drivers;
Power Is Measured on Output Driver Power Supply Only
(Pin 17, Pin 21, Pin 34, and Pin 38 for 1.8 V CMOS Mode or
on Pin 18 and Pin 37 for 3.3 V CMOS Mode); CLOAD = 80 pF
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
0
1
2
3
4
5
TIME (ns)
Figure 22. Output Waveform, HSTL (400 MHz)
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–1
0
1
2
3
4
TIME (ns)
Figure 23. Output Waveform, LVDS (400 MHz)
Data Sheet
3.4
3.0
2.6
2.2
1.8
1.4
1.0
2pF LOAD
0.6
10pF LOAD
0.2
–0.2
–1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TIME (ns)
Figure 24. Output Waveform,
3.3 V CMOS (100 MHz, Strong Mode)
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
2pF LOAD
10pF LOAD
0.1
–0.1
–1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TIME (ns)
Figure 25. Output Waveform, 1.8 V CMOS (100 MHz)
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
–5
2pF LOAD
10pF LOAD
5 15 25 35 45 55 65 75 85 95
TIME (ns)
Figure 26. Output Waveform, 3.3 V CMOS (20 MHz, Weak Mode)
Rev. 0 | Page 24 of 120