AD9559BCPZ Datasheet, PDF (50/120 Pages) Analog Devices – Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

AD9559
Communication Cycle—Instruction Plus Data
The AD9559 supports the long instruction mode only. The SPI
protocol consists of a two-part communication cycle. The first
part is a 16-bit instruction word that is coincident with the first
16 SCLK rising edges and a payload. The instruction word
provides the AD9559 serial control port with information
regarding
the
payload.
The
instruction
word
includes
the
R/W^E
A
A
bit that indicates the direction of the payload transfer (that is, a
read or write operation). The instruction word also indicates
the number of bytes in the payload and the starting register
address of the first payload byte.
Write
If the instruction word indicates a write operation, the payload
is written into the serial control port buffer of the AD9559. Data
bits are registered on the rising edge of SCLK. The length of the
transfer (1, 2, or 3 bytes or streaming mode) depends on the W0
and W1 bits (see Table 26) in the instruction byte. When not
streaming,
CS^E
A
A
can
be
deasserted
after
each
sequence
of
eight
bits
to stall the bus (except after the last byte, where it ends the cycle).
When
the
bus
is
stalled,
the
serial
transfer
resumes
when
CS^E
A
A
is
asserted.
Deasserting
the
CS^E
A
A
pin
on
a
nonbyte
boundary
resets
the
serial control port. Reserved or blank registers are not skipped
over automatically during a write sequence. Therefore, the user
must know what bit pattern to write to the reserved registers to
preserve proper operation of the part. Generally, it does not matter
what data is written to blank registers, but it is customary to use 0s.
Most of the serial port registers are buffered (see the
Buffered/Active Registers section for details on the difference
between buffered and active registers). Therefore, data written
into buffered registers does not take effect immediately. An
additional operation is needed to transfer buffered serial control
port contents to the registers that actually control the device.
This is accomplished with an IO_UPDATE operation, which is
performed in one of two ways. One method is to write a Logic 1
to Register 0x0005, Bit 0 (this bit is an autoclearing bit). The
other method is to use an external signal via an appropriately
programmed multifunction pin. The user can change as many
register bits as desired before executing an IO_UPDATE. The
IO_UPDATE operation transfers the buffer register contents to
their active register counterparts.
Read
If the instruction word indicates a read operation, the next N ×
8 SCLK cycles clock out the data from the address specified in
the instruction word. N is the number of data bytes read and
depends on the W0 and W1 bits of the instruction word. The
readback data is valid on the falling edge of SCLK. Blank registers
are not skipped over during readback.
Data Sheet
A readback operation takes data from either the serial control
port buffer registers or the active registers, as determined by
Register 0x0004, Bit 0.
SPI Instruction Word (16 Bits)
The
MSB
of
the
16-bit
instruction
word
is
R/W,^E
A
A
which
indicates
whether the instruction is a read or a write. The next two bits,
W1 and W0, indicate the number of bytes in the transfer (see
Table 26). The final 13 bits are the register address (A12 to A0),
which indicates the starting register address of the read/write
operation (see Table 28).
SPI MSB-/LSB-First Transfers
The AD9559 instruction word and payload can be MSB first or
LSB first. The default for the AD9559 is MSB first. The LSB-first
mode can be set by writing a 1 to Register 0x0000, Bit 6.
Immediately after the LSB-first bit is set, subsequent serial
control port operations are LSB first.
When MSB-first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant payload byte. Subsequent
data bytes must follow in order from high address to low
address. In MSB-first mode, the serial control port internal
address generator decrements for each data byte of the multi-
byte transfer cycle.
When Register 0x0000, Bit 6 = 1 (LSB first), the instruction and
data bytes must be written from LSB to MSB. Multibyte data
transfers in LSB-first format start with an instruction byte that
includes the register address of the least significant payload byte
followed by multiple data bytes. The serial control port internal
byte address generator increments for each byte of the multibyte
transfer cycle.
For multibyte MSB-first (default) I/O operations, the serial control
port register address decrements from the specified starting address
toward Address 0x0000. For multibyte LSB-first I/O operations,
the serial control port register address increments from the starting
address toward Address 0x1FFF. Reserved addresses are not
skipped during multibyte I/O operations; therefore, the user
should write the default value to a reserved register and 0s to
unmapped registers. Note that it is more efficient to issue a new
write command than to write the default value to more than
two consecutive reserved (or unmapped) registers.
Table 27. Streaming Mode (No Addresses Are Skipped)
Write Mode Address Direction Stop Sequence
LSB First
Increment
0x0000…0x1FFF
MSB First
Decrement
0x1FFF…0x0000
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