AD9520-2 Datasheet, PDF (9/84 Pages) Analog Devices – 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO

Timing Diagrams
t_CLK
CLK
t_PECL
t_CMOS
Figure 2. CLK/CLK to Clock Output Timing, Div = 1
DIFFERENTIAL
80%
20%
LVPECL
t_RP
t_FP
Figure 3. LVPECL Timing, Differential
AD9520-2
SINGLE-ENDED
80%
20%
CMOS
10pF LOAD
t_RC
t_FC
Figure 4. CMOS Timing, Single-Ended, 10 pF Load
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