AD9520-2 Datasheet, PDF (12/84 Pages) Analog Devices – 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO

AD9520-2
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Min Typ Max Unit Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R DIV = 1
54
fs rms Integration BW = 200 kHz to 5 MHz
77
fs rms Integration BW = 200 kHz to 10 MHz
109
fs rms Integration BW = 12 kHz to 20 MHz
79
fs rms Integration BW = 200 kHz to 5 MHz
114
fs rms Integration BW = 200 kHz to 10 MHz
163
fs rms Integration BW = 12 kHz to 20 MHz
124
fs rms Integration BW = 200 kHz to 5 MHz
176
fs rms Integration BW = 200 kHz to 10 MHz
259
fs rms Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min Typ Max Unit
CLK = 622.08 MHz
Any LVPECL Output = 622.08 MHz
Divide Ratio = 1
CLK = 622.08 MHz
Any LVPECL Output = 155.52 MHz
Divide Ratio = 4
CLK = 1000 MHz
Any LVPECL Output = 100 MHz
Divide Ratio = 10
CLK = 500 MHz
Any LVPECL Output = 100 MHz
Divide Ratio = 5
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 200 MHz
Any CMOS Output Pair = 100 MHz
Divide Ratio = 2
46
fs rms
64
fs rms
223
fs rms
209
fs rms
325
fs rms
Test Conditions/Comments
Distribution section only; does not include
PLL and VCO; measured at rising edge of
clock signal
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 12 kHz to 20 MHz
Calculated from SNR of ADC method
Broadband jitter
Calculated from SNR of ADC method
Broadband jitter
Distribution section only; does not include
PLL and VCO
Calculated from SNR of ADC method
Broadband jitter
Rev. 0 | Page 12 of 84