ADE7566_15 Datasheet, PDF (85/152 Pages) Analog Devices – Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
STANDARD 8052 SFRs
Power Control Register (PCON, Address 0x87)
The standard 8052 SFRs include the accumulator (ACC), B,
PSW, DPTR, and SP SFRs, as described in the Basic 8052
Registers section. The 8052 also defines standard timers, serial
port interfaces, interrupts, I/O ports, and power-down modes.
Timer SFRs
The 8052 contains three 16-bit timers: the identical Timer 0 and
Timer 1, as well as a Timer 2. These timers can also function as
event counters. Timer 2 has a capture feature in which the value
of the timer can be captured in two 8-bit registers upon the
assertion of an external input signal (see Table 112 and the
Timers section).
Serial Port SFRs
The full-duplex serial port peripheral requires two registers, one
for setting up the baud rate and other communication parameters,
and another byte for the transmit/receive buffer. The ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 also
provide enhanced serial port functionality with a dedicated timer
for baud rate generation with a fractional divisor and additional
error detection. See Table 139 and the UART Serial Interface
section.
The 8052 core defines two power-down modes: power-down and
idle. The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 enhance the power control capability of the traditional
8052 MCU with additional power management functions. The
POWCON register is used to define power control-specific
functionality for the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569. The program control SFR (PCON, Address
0x87) is not bit addressable. See the Power Management section.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 have many other peripherals not standard to the
8052 core:
• ADE energy measurement DSP
• RTC
• LCD driver
• Battery switchover/power management
• Temperature ADC
• Battery ADC
• SPI/I²C communication
• Flash memory controller
• Watchdog timer
Interrupt SFRs
There is a two-tiered interrupt system standard in the 8052 core.
The priority level for each interrupt source is individually
selectable as high or low. The ADE7116/ADE7156/ADE7166/
ADE7169/ADE7566/ADE7569 enhance this interrupt system
by creating, in essence, a third interrupt tier for a highest
priority power supply management interrupt (PSM). See
the Interrupt System section.
I/O Port SFRs
The 8052 core supports four I/O ports, P0 through P3, where
Port 0 and Port 2 are typically used for access to external code
and data spaces. The ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569, unlike standard 8052 products, provide
internal nonvolatile flash memory so that an external code
space is unnecessary. The on-chip LCD driver requires many
pins, some of which are dedicated to LCD functionality, and
others that can be configured as LCD or general-purpose I/O.
Due to the limited number of I/O pins, the
ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569
do not allow access to external code and data spaces.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 provide 20 pins that can be used for general-purpose
I/O. These pins are mapped to Port 0, Port 1, and Port 2 and are
accessed through three bit-addressable 8052 SFRs: P0, P1, and
P2. Another enhanced feature of these parts is that the weak
pull-ups standard on 8052 Port 1, Port 2, and Port 3 can be
disabled to make open-drain outputs, as is standard on Port 0.
The weak pull-ups can be enabled on a pin-by-pin basis. See the
I/O Ports section.
MEMORY OVERVIEW
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 contain three memory blocks:
• 16 kB of on-chip Flash/EE program and data memory
• 256 bytes of general-purpose RAM
• 256 bytes of internal extended RAM (XRAM)
The 256 bytes of general-purpose RAM share the upper 128 bytes
of its address space with the SFRs. All of the memory spaces are
shown in Figure 81. The addressing mode specifies which
memory space to access.
General-Purpose RAM
General-purpose RAM resides in Memory Location 0x00
through Memory Location 0xFF. It contains the register banks.
0x30
BANKS
SELECTED
VIA
BITS IN PSW
11
0x20
0x18
10
0x10
01
0x08
00
0x00
0x7F
0x2F
0x1F
0x17
0x0F
0x07
GENERAL-PURPOSE
AREA
BIT-ADDRESSABLE
(BIT ADDRESSES)
FOUR BANKS OF EIGHT
REGISTERS R0 TO R7
RESET VALUE OF
STACK POINTER
Figure 83. Lower 128 Bytes of Internal Data Memory
Rev. B | Page 85 of 152