ADE7566_15 Datasheet, PDF (100/152 Pages) Analog Devices – Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
LCD DRIVER
Using shared pins, the LCD module is capable of directly driving
an LCD panel of 17 × 4 segments without compromising any
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
functions. It is capable of driving LCDs with 2×, 3×, and 4× multi-
plexing. The LCD waveform voltages generated through internal
charge pump circuitry support up to 5 V LCDs for the ADE7156/
ADE7166/ADE7169/ADE7566/ADE7569. An external resistor
ladder for LCD waveform voltage generation is also supported.
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has an embedded LCD control circuit, driver, and
power supply circuit. The LCD module is functional in all
operating modes (see the Operating Modes section).
LCD REGISTERS
There are six LCD control registers that configure the driver for
the specific type of LCD in the end system and set up the user
display preferences. The LCD configuration SFR (LCDCON,
Address 0x95), LCD Configuration X SFR (LCDCONX,
Address 0x9C), and LCD Configuration Y SFR (LCDCONY,
Address 0xB1) contain general LCD driver configuration
information including the LCD enable and reset, as well as the
method of LCD voltage generation and multiplex level. The
LCD clock SFR (LCDCLK, Address 0x96) configures timing
settings for LCD frame rate and blink rate. LCD pins are
configured for LCD functionality in the LCD segment enable
SFR (LCDSEGE, Address 0x97) and the LCD Segment Enable 2
SFR (LCDSEGE2, Address 0xED).
Table 87. LCD Driver SFRs
SFR Address
R/W
0x95
R/W
0x96
R/W
0x97
R/W
0x9C
R/W
0xAC
R/W
0xAE
R/W
0xB1
R/W
0xED
R/W
Mnemonic
LCDCON
LCDCLK
LCDSEGE
LCDCONX
LCDPTR
LCDDAT
LCDCONY
LCDSEGE2
Description
LCD configuration SFR (see Table 88).
LCD clock (see
Table 92).
LCD segment Enable (see Table 95).
LCD configuration X (see Table 89).
LCD pointer (see Table 96).
LCD data (see Table 97).
LCD configuration Y (see Table 91).
LCD segment Enable 2 (see Table 98).
Table 88. LCD Configuration SFR (LCDCON, Address 0x95)
Bit Mnemonic Default Description
7
LCDEN
0
LCD enable. If this bit is set, the LCD driver is enabled.
6
LCDRST
0
LCD data registers reset. If this bit is set, the LCD data registers are reset to 0.
5
BLINKEN 0
Blink mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by the
BLKMOD and BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96).
4
LCDPSM2 0
Forces LCD off when in PSM2 (sleep) mode. Note that the internal voltage reference must be enabled by
setting the REF_BAT_EN bit in the Peripheral Configuration SFR (PERIPH, Address 0xF4) to allow LCD
operation in PSM2 mode.
LCDPSM2 Result
0
The LCD is disabled or enabled in PSM2 by the LCDEN bit
1
The LCD is disabled in PSM2 regardless of LCDEN setting
3
CLKSEL
0
LCD clock selection.
CLKSEL
Result
0
fLCDCLK = 2048 Hz
1
fLCDCLK = 128 Hz
2
BIAS
0
Bias mode.
BIAS
Result
0
1/2
1
1/3
[1:0] LMUX
0
LCD multiplex level.
LMUX
Result
00
Reserved.
01
2× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as FP28.
10
3× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as COM2.
11
4× multiplexing. FP27/COM3 is used as COM3, and FP28/COM2 is used as COM2.
Rev. B | Page 100 of 152