ADE7566_15 Datasheet, PDF (141/152 Pages) Analog Devices – Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
I²C RECEIVE AND TRANSMIT FIFOS
The I²C peripheral has a 4-byte receive FIFO and a 4-byte
transmit FIFO. The buffers reduce the overhead associated with
using the I²C peripheral. Figure 115 shows the operation of the
I²C receive and transmit FIFOs.
The Tx FIFO can be loaded with four bytes to be transmitted to
the slave at the beginning of a write operation. When the
transmit FIFO is empty, the I²C transmit interrupt flag is set,
and the PC vectors to the I²C interrupt vector if this interrupt is
enabled. If a new byte is not loaded into the Tx FIFO before it is
needed in the transmit shift register, the communication stops.
An error, such as not receiving an acknowledge, also causes the
communication to terminate. In case of an error during a write
operation, the Tx FIFO is flushed.
The Rx FIFO allows four bytes to be read in from the slave
before the MCU has to read the data. A receive interrupt can
be generated after each byte is received or when the Rx FIFO
is full. If the peripheral is reading from a slave address, the
communication stops when the number of received bytes equals
the number set in the I2CRCT bits. An error, such as not
receiving an acknowledge, also causes the communication to
terminate.
CODE TO FILL Tx FIFO:
MOV I²CTx, TxDATA1
MOV I²CTx, TxDATA2
MOV I²CTx, TxDATA3
MOV I²CTx, TxDATA4
CODE TO READ Rx FIFO:
MOV A, I²CRx; RESULT: A = RxDATA1
MOV A, I²CRx; RESULT: A = RxDATA2
MOV A, I²CRx; RESULT: A = RxDATA3
MOV A, I²CRx; RESULT: A = RxDATA4
I²CTx
I²CRx
4 BYTE FIFO
TxDATA4
TxDATA3
TxDATA2
TxDATA1
4 BYTE FIFO
RxDATA1
RxDATA2
RxDATA3
RxDATA4
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
Figure 115. I²C FIFO Operation
Rev. B | Page 141 of 152