ADV7391_15 Datasheet, PDF (83/108 Pages) Analog Devices – Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

Data Sheet
DISPLAY
ADV7390/ADV7391/ADV7392/ADV7393
VERTICAL BLANK
DISPLAY
522 523 524 525 1
HSYNC
VSYNC
DISPLAY
2
3
4
EVEN FIELD
5
6
7
8
ODD FIELD
VERTICAL BLANK
9
10
11
20
21
22
DISPLAY
HSYNC
VSYNC
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
ODD FIELD
EVEN FIELD
Figure 111. SD Timing Mode 2, Slave Option, NTSC
DISPLAY
VERTICAL BLANK
283 284 285
DISPLAY
622 623 624 625
1
2
3
4
5
6
7
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
21
22
23
DISPLAY
HSYNC
309 310 311 312 313 314 315 316 317 318 319 320
VSYNC
ODD FIELD
EVEN FIELD
Figure 112. SD Timing Mode 2, Slave Option, PAL
334 335 336
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV739x can generate horizontal and vertical synchronization signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are output on the
HSYNC and VSYNC pins, respectively.
HSYNC
VSYNC
PIXEL
DATA
Cb Y Cr Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 113. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
Rev. H | Page 83 of 108