ADV7391_15 Datasheet, PDF (58/108 Pages) Analog Devices – Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

ADV7390/ADV7391/ADV7392/ADV7393
To add a –7 IRE brightness level to a PAL signal, write 0x72 to
Subaddress 0xA1.
0 × (SD Brightness Value) =
0 × (IRE Value × 2.075631) =
0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b
0001110b into twos complement = 1110010b = 0x72
Table 49. Sample Brightness Control Values¹
Setup Level
(NTSC) with
Pedestal
Setup Level
Setup
(NTSC) Without Level
Pedestal
(PAL)
22.5 IRE
15 IRE
15 IRE
15 IRE
7.5 IRE
7.5 IRE
7.5 IRE
0 IRE
0 IRE
0 IRE
−7.5 IRE
−7.5 IRE
Brightness
Control Value
0x1E
0x0F
0x00
0x71
1 _{Values in the range of 0x3F to 0x44 may result in an invalid output signal.}
SD INPUT STANDARD AUTODETECTION
Subaddress 0x87, Bit 5
The ADV739x includes an SD input standard autodetect feature
that can be enabled by setting Subaddress 0x87, Bits[5:1].
When enabled, the ADV739x can automatically identify an
NTSC or a PAL B/D/G/H/I input stream. The ADV739x
automatically updates the subcarrier frequency registers with
the appropriate value for the identified standard. The ADV739x
is also configured to correctly encode the identified standard.
The SD standard bits (Subaddress 0x80, Bits[1:0]) and the
subcarrier frequency registers are not updated to reflect the
identified standard. All registers retain their default or user-
defined values.
DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD;
Subaddress 0x88, Bit 2 for SD
Double-buffered registers are updated once per field. Double
buffering improves overall performance because modifications
to register settings are not be made during active video but take
effect prior to the start of the active video on the next field.
Using Subaddress 0x33, Bit 7, double buffering can be activated
on the following ED/HD registers: the ED/HD Gamma A and
Gamma B curves and ED/HD CGMS registers.
Using Subaddress 0x88, Bit 2, double buffering can be activated
on the following SD registers: the SD Gamma A and Gamma B
curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD
closed captioning, and SD Macrovision Bits[5:0]
(Subaddress 0xE0, Bits[5:0]).
Data Sheet
PROGRAMMABLE DAC GAIN CONTROL
Subaddress 0x0B
It is possible to adjust the DAC output signal gain up or down
from its absolute level. This is illustrated in Figure 70.
DAC 1 to DAC 3 are controlled by Register 0x0B.
In Case A of Figure 70, the video output signal is gained. The
absolute level of the sync tip and the blanking level increase
with respect to the reference video output signal. The overall
gain of the signal is increased from the reference signal.
In Case B of Figure 70, the video output signal is reduced. The
absolute level of the sync tip and the blanking level decrease
with respect to the reference video output signal. The overall
gain of the signal is reduced from the reference signal.
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0x0B
700mV
300mV
CASE B
700mV
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0B
300mV
Figure 70. Programmable DAC Gain—Positive and Negative Gain
The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC gain control feature can change this
output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).
Rev. H | Page 58 of 108