ADV7391_15 Datasheet, PDF (72/108 Pages) Analog Devices – Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
TYPICAL APPLICATIONS CIRCUITS
V_{DD_IO}
FERRITE BEAD
33µF
10µF
PV_DD
GND_IO
GND_IO
FERRITE BEAD
33µF
10µF
PGND
PGND
FERRITE BEAD
V_AA
33µF
10µF
AGND
AGND
FERRITE BEAD
V_DD
33µF
10µF
DGND
DGND
0.1µF
GND_IO
0.1µF
PGND
0.1µF
AGND
0.1µF
DGND
0.01µF
GND_IO
V_{DD_IO} POWER
SUPPLY
DECOUPLING
0.01µF
PGND
PV_DD POWER
SUPPLY
DECOUPLING
0.01µF
AGND
1µF ^VAA ^POWER
SUPPLY
AGND ^DECOUPLING
0.01µF
DGND
V_DD POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
NOTES
1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED
TO THE COMP, R_SET AND DAC OUTPUT PINS SHOULD BE LOCATED
CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV739x.
2. THE I²C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN:
ALSB = 0, I²C DEVICE ADDRESS = 0xD4 (ADV7390/ADV7392) OR
0x54 (ADV7391/ADV7393)
ALSB = 1, I²C DEVICE ADDRESS = 0xD6 (ADV7390/ADV7392) OR
0x56 (ADV7391/ADV7393)
3. THE RESISTOR CONNECTED TO THE R_SET PIN SHOULD HAVE A 1%
TOLERANCE.
4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULL-
DRIVE (R_SET = 510Ω, R_L = 37.5Ω).
PIXEL PORT INPUTS
CONTROL
INPUTS/OUTPUTS
P0
P1
P2
P3
P4
P5
ADV739x
P6
P7
P8
P9
P10
P11 _ADV7392/
P12 ADV7393
P13 ^ONLY
P14
P15
HSYNC
VSYNC
COMP
R_SET
V_AA
2.2nF
510Ω
AGND
DAC 1
DAC 2
DAC 3
DAC1 TO DAC3 FULL DRIVE OPTION
(RECOMMENDED)
OPTIONAL LPF
OPTIONAL LPF
DAC 1
DAC 2
75Ω
75Ω
DAC 3
OPTIONAL LPF
75Ω
AGND AGND AGND
R_SET
DAC 1
CLOCK INPUT
CLKIN
I2C PORT
SDA
SCL
EXTERNAL LOOP FILTER
PV_DD
12nF
150nF _170Ω
RESET
EXT_LF
ALSB
TIE EITHER LOW
OR HIGH
DAC 2
DAC 3
LOOP FILTER COMPONENTS
SHOULD BE LOCATED
CLOSE TO THE EXT_LF
PIN AND ON THE
SAME SIDE OF THE PCB
AS THE ADV739x.
AGND
PGND
DGND
DGND
GND_IO
AGND PGND DGND DGND GND_IO
Figure 93. ADV739x (LFCSP) Typical Applications Circuit
DAC1 TO DAC3 LOW DRIVE OPTION
4.12kΩ
AGND
ADA4411-3
75Ω
LPF
300Ω
AGND
ADA4411-3
75Ω
LPF
300Ω
AGND
ADA4411-3
75Ω
LPF
300Ω
AGND
DAC 1
DAC 2
DAC 3
Rev. H | Page 72 of 108