ADSP-BF542_1 Datasheet, PDF (82/100 Pages) Analog Devices – Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
ATAPI Ultra DMA Data-Out Transfer Timing
Table 61 and Figure 56 through Figure 59 describes the ATAPI
ultra DMA data-out transfer timing.
Table 61. ATAPI Ultra DMA Data-Out Transfer Timing
ATAPI Parameter
ATAPI_ULTRA_TIM_x Timing
Register Setting¹
Timing Equation
t_CYC2
Cycle time
TDVS, TCYC_TDVS
t_2CYC
Two cycle time
TDVS, TCYC_TDVS
t_DVS
Data valid setup time at sender
TDVS
t_DVH
Data valid hold time at sender
TCYC_TDVS
t_CVS
CRC word valid setup time at host
TDVS
t_CVH
CRC word valid hold time at host
TACK
t_DZFS
Time from data output released-to-driving to first TDVS
strobe timing
(TDVS + TCYC_TDVS) × t_SCLK
2 × (TDVS + TCYC_TDVS) × t_SCLK
TDVS × t_SCLK – (t_SK1 + t_SK2)
TCYC_TDVS × t_SCLK – (t_SK1 + t_SK2)
TDVS × t_SCLK – (t_SK1 + t_SK2)
TACK × t_SCLK – (t_SK1 + t_SK2)
TDVS × t_SCLK – (t_SK1 + t_SK2)
t_LI
Limited interlock time
N/A
t_MLI
Interlock time with minimum
TMLI
t_ENV3
ATAPI_DMACK to ATAPI_DIOR/DIOW
TENV
t_RFS
Ready to final strobe time
N/A
t_ACK
Setup and Hold time for ATAPI_DMACK
TACK
t_SS
Time from STROBE edge to assertion of ATAPI_DIOW TSS
2 × t_BD + 2 × t_SCLK + t_OD
TMLI × t_SCLK – (t_SK1 + t_SK2)
(TENV × t_SCLK) +/– (t_SK1 + t_SK2)
2 × t_BD + 2 × t_SCLK + t_OD
TACK × t_SCLK – (t_SK1 + t_SK2)
TSS × t_SCLK – (t_SK1 + t_SK2)
1 _{ATAPI Timing Register Setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation.}
2 _{ATA/ATAPI-6 compliant functionality with limited speed.}
3 _{This timing equation can be used to calculate both the minimum and maximum tENV.}
Rev. C | Page 82 of 100 | February 2010