ADSP-BF542_1 Datasheet, PDF (70/100 Pages) Analog Devices – Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Table 51. SD/SDIO Controller Timing (High Speed Mode)
Parameter
Timing Requirements
t_ISU
SD_Dx and SD_CMD Input Setup Time
t_IH
SD_Dx and SD_CMD Input Hold Time
Switching Characteristics
f_PP
SD_CLK Frequency During Data Transfer Mode¹
t_WL
SD_CLK Low Time
t_WH
SD_CLK High Time
t_TLH
SD_CLK Rise Time
t_THL
SD_CLK Fall Time
t_ODLY
SD_Dx and SD_CMD Output Delay Time During Data Transfer Mode
t_OH
SD_Dx and SD_CMD Output Hold Time
1 _tPP=1/fPP
Min
Max
Unit
7.2
ns
2
ns
0
40
MHz
9.5
ns
9.5
ns
3
ns
3
ns
2
ns
2.5
ns
SD_CLK
INPUT
t_PP
t_THL
t_WL
t_TLH
t_WH
t_ISU
t_IH
t_ODLY
t_OH
OUTPUT
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 44. SD/SDIO Controller Timing (High Speed Mode)
V_{OH (MIN)}
V_{OL (MAX)}
Rev. C | Page 70 of 100 | February 2010