ADSP-BF544_15 Datasheet, PDF (81/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
ATAPI Ultra DMA Data-In Transfer Timing
Table 60 and Figure 53 through Figure 56 describe the ATAPI
ultra DMA data-in data transfer timing. The material in these
figures is adapted from ATAPI-6 (INCITS 361-2002[R2007]
and is used with permission of the American National Stan-
dards Institute (ANSI) on behalf of the Information Technology
Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-
2002[R2007] can be purchased from ANSI.
Table 60. ATAPI Ultra DMA Data-In Transfer Timing
ATAPI Parameter
ATAPI_ULTRA_TIM_x Timing
Register Setting¹
Timing Equation
t_DS
Data setup time at host
t_DH
Data hold time at host
t_CVS
CRC word valid setup time at host
t_CVH
CRC word valid hold time at host
t_LI
Limited interlock time
t_MLI
Interlock time with minimum
N/A
N/A
TDVS
TACK
N/A
TZAH, TCVS
T_SK3 + t_SUDU
T_SK3 + t_HDU
TDVS × t_SCLK – (t_SK1 + t_SK2)
TACK × t_SCLK – (t_SK1 + t_SK2)
2 × t_BD + 2 × t_SCLK + t_OD
(TZAH + TCVS) × t_SCLK – (4 × t_BD + 4 × t_SCLK + 2 × t_OD)
t_AZ
Maximum time allowed for output drivers to N/A
0
release
t_ZAH
Minimum delay time required for output
TZAH
2 × t_SCLK + TZAH × t_SCLK + t_SCLK
t_ENV2
ATAPI_DMACK to ATAPI_DIOR/DIOW
TENV
(TENV × t_SCLK) +/– (t_SK1 + t_SK2)
t_RP
ATAPI_DMACK to ATAPI_DIOR/DIOW
TRP
TRP × t_SCLK – (t_SK1 + t_SK2 + t_SK4)
t_ACK
Setup and hold times for ATAPI_DMACK
TACK
TACK × t_SCLK – (t_SK1 + t_SK2)
1 _{ATAPI Timing Register Setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation.}
2 _{This timing equation can be used to calculate both the minimum and maximum tENV.}
Rev. E | Page 81 of 102 | March 2014