ADSP-BF544_15 Datasheet, PDF (66/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 45 and Figure 39 describe SPI port slave operations.
Table 45. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t_SPICHS
SPIxSCK High Period
t_SPICLS
SPIxSCK Low Period
t_SPICLK
SPIxSCK Period
t_HDS
Last SPIxSCK Edge to SPIxSS Not Asserted
t_SPITDS
Sequential Transfer Delay
t_SDSCI
SPIxSS Assertion to First SPIxSCK Edge
t_SSPID
Data Input Valid to SPIxSCK Edge (Data Input Setup)
t_HSPID
SPIxSCK Sampling Edge to Data Input Invalid
Switching Characteristics
t_DSOE
t_DSDHI
t_DDSPID
t_HDSPID
SPIxSS Assertion to Data Out Active
SPIxSS Deassertion to Data High Impedance
SPIxSCK Edge to Data Out Valid (Data Out Delay)
SPIxSCK Edge to Data Out Invalid (Data Out Hold)
Min
Max
2t_SCLK – 1.5
2t_SCLK – 1.5
4t_SCLK
2t_SCLK –1.5
2t_SCLK –1.5
2t_SCLK –1.5
1.6
1.6
0
8
0
8
10
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
SPIxMISO
(OUTPUT)
CPHA = 1
SPIxMOSI
(INPUT)
t_SDSCI
t_SPICLS
t_SPICHS
t_DSOE
t_DDSPID
t_HDSPID
t_SSPID
t_HSPID
t_DSOE
SPIxMISO
(OUTPUT)
CPHA = 0
SPIxMOSI
(INPUT)
t_HDSPID
t_SPICLK
t_DDSPID
t_HDS
t_SPITDS
t_DSDHI
t_DDSPID
t_SSPID
t_DSDHI
t_HSPID
Figure 39. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. E | Page 66 of 102 | March 2014