ADSP-BF544_15 Datasheet, PDF (27/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Table 11. Pin Descriptions (Continued)
Pin Name
I/O¹ Function (First/Second/Third/Fourth)
Driver
Type²
Port C: GPIO/SPORT0/SD Controller/MXVR (MOST)
PC0 / TFS0
I/O GPIO/SPORT0 Transmit Frame Sync
C
PC1 / DT0SEC / MMCLK
I/O GPIO/SPORT0 Transmit Data Secondary/MXVR Master Clock
C
PC2 / DT0PRI
I/O GPIO/SPORT0 Transmit Data Primary
C
PC3 / TSCLK0
I/O GPIO/SPORT0 Transmit Serial Clock
A
PC4 / RFS0
I/O GPIO/SPORT0 Receive Frame Sync
C
PC5 / DR0SEC/MBCLK
I/O GPIO/SPORT0 Receive Data Secondary/MXVR Bit Clock
C
PC6 / DR0PRI
I/O GPIO/SPORT0 Receive Data Primary
C
PC7 / RSCLK0
I/O GPIO/SPORT0 Receive Serial Clock
C
PC8 / SD_D0
I/O GPIO/SD Data Bus
A
PC9 / SD_D1
I/O GPIO/SD Data Bus
A
PC10 / SD_D2
I/O GPIO/SD Data Bus
A
PC11 / SD_D3
I/O GPIO/SD Data Bus
A
PC12 / SD_CLK
I/O GPIO/SD Clock Output
A
PC13 / SD_CMD
I/O GPIO/SD Command
A
Port D: GPIO / PPI0–2/SPORT 1/ Keypad/ Host DMA
PD0/PPI1_D0/HOST_D8/ TFS1/PPI0_D18
I/O GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Frame Sync/PPI0 Data C
PD1/PPI1_D1/HOST_D9/ DT1SEC/PPI0_D19
I/O GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Data Secondary/PPI0 Data C
PD2/PPI1_D2/HOST_D10/ DT1PRI/PPI0_D20
I/O GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Data Primary/PPI0 Data C
PD3/PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21
I/O GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Serial Clock/PPI0 Data A
PD4 / PPI1_D4 / HOST_D12 / RFS1 / PPI0_D22
I/O GPIO/PPI1 Data/Host DMA/SPORT1 Receive Frame Sync/PPI0 Data
C
PD5/PPI1_D5 / HOST_D13 / DR1SEC / PPI0_D23
I/O GPIO/PPI1 Data/Host DMA/SPORT1 Receive Data Secondary/PPI0 Data C
PD6 / PPI1_D6 / HOST_D14 / DR1PRI
I/O GPIO/PPI1 Data/Host DMA/SPORT1 Receive Data Primary
C
PD7 / PPI1_D7 / HOST_D15 / RSCLK1
I/O GPIO/PPI1 Data /Host DMA/SPORT1 Receive Serial Clock
A
PD8/PPI1_D8/HOST_D0/ PPI2_D0/KEY_ROW0 I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Row Input
A
PD9 / PPI1_D9 / HOST_D1 / PPI2_D1 / KEY_ROW1
I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Row Input
A
PD10/PPI1_D10/HOST_D2/PPI2_D2/KEY_ROW2 I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Row Input
A
PD11/PPI1_D11/HOST_D3/PPI2_D3/KEY_ROW3 I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Row Input
A
PD12/PPI1_D12/HOST_D4/PPI2_D4/KEY_COL0 I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output
A
PD13/PPI1_D13/HOST_D5/PPI2_D5/KEY_COL1 I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output
A
PD14/PPI1_D14/HOST_D6/PPI2_D6/KEY_COL2 I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output
A
PD15/PPI1_D15/HOST_D7/PPI2_D7/KEY_COL3 I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output
A
Rev. E | Page 27 of 102 | March 2014