ADV7393_15 Datasheet, PDF (80/108 Pages) Analog Devices – Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All
timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after
each line during active picture and retrace. If the VSYNC and HSYNC pins are not used, they should be tied to VDD_IO when using this
mode.
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
EAV CODE
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
4 CLOCK
0F FAAA
0F FBBB
ANCILLARY DATA
(HANC)
268 CLOCK
SAV CODE
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
CY
b
C
r
YC
b
Y
C
r
Y
C
b
4 CLOCK
1440 CLOCK
4 CLOCK
280 CLOCK
END OF ACTIVE
VIDEO LINE
Figure 104. SD Timing Mode 0, Slave Option
4 CLOCK
1440 CLOCK
START OF ACTIVE
VIDEO LINE
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV739x generates H and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is output
on HSYNC and the F bit is output on VSYNC.
DISPLAY
VERTICAL BLANK
DISPLAY
522 523 524 525
1
2
3
4
5
6
7
8
9
10
11
H
F
EVEN FIELD ODD FIELD
DISPLAY
VERTICAL BLANK
20
21
22
DISPLAY
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
H
F
ODD FIELD EVEN FIELD
Figure 105. SD Timing Mode 0, Master Option, NTSC
283 284 285
Rev. H | Page 80 of 108