ADV7393_15 Datasheet, PDF (46/108 Pages) Analog Devices – Low Power, Chip Scale, 10-Bit SD/HD Video Encoder

ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
ADV7390/ADV7391 INPUT CONFIGURATION
The ADV7390/ADV7391 support a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7390/ADV7391 default to standard definition
(SD) mode on power-up. Table 35 provides an overview of all
possible input configurations. Each input mode is described in
detail in this section. Note that the WLCSP option is only
configured to support SD as shown in Figure 51.
Table 35. ADV7390/ADV7391 Input Configuration
Input Mode
P7 P6 P5 P4 P3 P2 P1 P0
000 SD
YCrCb
010 ED/HD-DDR
YCrCb
111 ED (at 54 MHz)
YCrCb
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
SD YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 27 MHz. A 27 MHz clock signal must be
provided on the CLKIN pin. If required, external synchroni-
zation signals can be provided on the HSYNC and VSYNC pins.
Embedded EAV/SAV timing codes are also supported. The
ITU-R BT.601/656 input standard is supported. The interleaved
pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB.
MPEG2
DECODER
2
27MHz
ADV7390/
ADV7391
VSYNC,
HSYNC
CLKIN
YCrCb
8
P[7:0]
Figure 51. SD Example Application
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 010
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in an interleaved 4:2:2 format over an 8-bit DDR
bus. The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin P7 to Pin P0 on either the rising or falling edge of CLKIN.
Pin P0 is the LSB.
The CrCb pixel data is also input on Pin P7 to Pin P0 on the
opposite edge of CLKIN. Pin P0 is the LSB.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 52
and Figure 53).
CLKIN
P[7:0] 3FF 00
00
XY Cb0 Y0 Cr0 Y1
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
CLKIN
P[7:0]
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
MPEG2
DECODER
YCrCb
ADV7390/
ADV7391
CLKIN
YCrCb ⁸
INTERLACED TO
PROGRESSIVE
2
P[7:0]
VSYNC,
HSYNC
Figure 54. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
CLKIN
P[7:0] _{3FF 00}
00
XY Cb0 Y0 Cr0 Y1
Figure 55. ED (at 54 MHz) Input Sequence (EAV/SAV)
Rev. H | Page 46 of 108