HMC5805A Datasheet, PDF (8/10 Pages) Analog Devices – High P1dB Output Power: 24.5 dBm

HMC5805ALS6
v01.1216
GaAs pHEMT MMIC 0.25 WATT POWER AMPLIFIER
DC - 40 GHz
Application Information
BIASING PROCEDURES:
DC bias must be applied to the drain via an RF choke/inductor connection to the RFOUT/VDD pin. Gate bias must be applied to
VGG1 and VGG2. Capacitive bypassing is recommended for all of the DC bias pins and AC terminations to ground are recom-
mended for ACG1-ACG4, as shown in the Application Circuit.
The recommended bias sequence during power-up is as follows:
1. Set VGG1 to −2.0 V to pinch off the channels of the lower FETs.
2. Set VDD to 10.0 V. Because the lower FETs are pinched off, IDQ remains very low upon application of VDD.
3. Set VGG2 to 3.5 V.
3. Adjust VGG1 to be more positive until a quiescent drain current of 175 mA has been obtained.
4. Apply the RF input signal.
The recommended bias sequence during power-down is as follows:
1. Turn off the RF input signal.
2. Set VGG1 to −2.0 V to pinch off the channels of the lower FETs.
3. Set VGG2 to 0 V.
4. Set VDD to 0 V.
5. Set VGG1 to 0 V.
Power-up and power-down sequences may differ from the ones described, though care must always be taken to
ensure adherence to the values shown in the Absolute Maximum Ratings.
Unless otherwise noted, all measurements and data shown were taken using the typical application circuit as config-
ured on our evaluation board. The bias conditions shown in the specifications section are the operating points recom-
mended to optimize the overall performance. Operation using other bias conditions may provide performance that
differs from what is shown in this data sheet.
Application Circuit

NOTE 1: Drain Bias (Vdd) must be applied through a broadband bias tee
with low series resistance and capable of providing 250 mA
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Phone: [phone] • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
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