HMC5805A Datasheet, PDF (10/10 Pages) Analog Devices – High P1dB Output Power: 24.5 dBm

HMC5805ALS6
v01.1216
GaAs pHEMT MMIC 0.25 WATT POWER AMPLIFIER
DC - 40 GHz
Theory of Operation
The HMC5805ALS6 is a GaAs, pHEMT, MMIC power amplifier. Its basic architecture is that of a cascode distributed
amplifier which allows for control of DC bias for a drain and two gates. The cascode distributed architecture uses a
fundamental cell consisting of a stack of two field effect transistors (FETs) with the source of the upper FET connected
to the drain of the lower FET. The fundamental cell is then duplicated several times, with a transmission line feed-
ing the RFIN signal to the gates of the lower FETs and a separate transmission line interconnecting the drains of the
upper FETs and routing the amplified signal to the RFOUT/VDD pin. Additional circuit design techniques are used
around each cell to optimize the overall performance for broadband operation. The major benefit of this architecture
is that high performance is maintained across a bandwidth far greater than what a single instance of the fundamen-
tal cell would provide. Additionally, ACG1-ACG4 provide access to internal nodes which, when provided with the
recommended AC terminations to ground, ensure that the overall response remains flat across the widest possible
frequency range. A simplified Schematic of Architecture is shown in below.
Schematic of Architecture
ACG2
ACG1
T-Line
RFOUT/VDD
VGG2
T-Line
RFIN
VGG1
ACG4 ACG3
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