AD9575 Datasheet, PDF (8/16 Pages) Analog Devices – Network Clock Generator, Two Outputs

AD9575
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GNDA 1
VDDA 2
VDDX 3
XO1 4
XO2 5
GNDX 6
GNDA 7
VDDA 8
16 SEL0
15 GND
AD9575
TOP VIEW
(Not to Scale)
14 LVDS/LVPECL OUT
13 LVDS/LVPECL OUT
12 VDD
11 VDD_CMOS
10 CMOS OUT/SEL1
9 GND_CMOS
Figure 4. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic
Description
1, 7
GNDA
Analog Ground.
2, 8
VDDA
Analog Power Supply (3.3 V).
3
VDDX
Crystal Oscillator Power Supply.
4, 5
XO1, XO2
External Crystal.
6
GNDX
Crystal Oscillator Ground.
9
GND_CMOS
Ground for LVCMOS Output.
10
CMOS OUT/SEL1
LVCMOS Output/Output Frequency Select.
11
VDD_CMOS
Power Supply for LVCMOS Output.
12
VDD
Power Supply for LVDS or LVPECL Output.
13
LVDS/LVPECL OUT
Complementary LVDS or LVPECL Output.
14
LVDS/LVPECL OUT
LVDS or LVPECL Output.
15
GND
Ground for LVDS or LVPECL Output.
16
SEL0
Output Frequency Select.
Table 12. Output Frequency Selection¹
Mode
XTAL
SEL0
1
25 MHz
GND
2
25 MHz
VDD
3
25.78125 MHz
VDD
4
25 MHz
NC
5
25 MHz
15 kΩ pull-up
6
25 MHz
15 kΩ pull-up
7
25 MHz
VDD
8
19.44 MHz
VDD
SEL1
X²
GND
GND
X²
VDD
GND
VDD
No connect
1 _{The AD9575 must be power-cycled if the select pin voltages are altered.}
2 _{X = in Mode 1 and Mode 4, Pin 10 is configured as a LVCMOS output by forcing Pin16 to GND.}
LVDS/LVPECL Output
100 MHz
156.25 MHz
161.132812 MHz
125 MHz
159.375 MHz
312.5 MHz
106.25 MHz
155.52 MHz
LVCMOS Output
33.33 MHz
High-Z
High-Z
62.5 MHz
High-Z
High-Z
High-Z
High-Z
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