AD9575 Datasheet, PDF (13/16 Pages) Analog Devices – Network Clock Generator, Two Outputs

3.3V
LVPECL
200Ω
0.1nF
0.1nF
DIFFERENTIAL
(COUPLED)
100Ω
200Ω
3.3V
LVPECL
Figure 19. LVPECL with Parallel Transmission Line
LVDS CLOCK DISTRIBUTION
The AD9575 is also available with low voltage differential
signaling (LVDS) outputs. LVDS uses a current mode output
stage with a factory programmed current level. The normal
value (default) for this current is 3.5 mA, which yields a 350 mV
output swing across a 100 Ω resistor. The LVDS outputs meet or
exceed all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 20.
50Ω
LVDS
100Ω
LVDS
50Ω
Figure 20. LVDS Output Termination
See the AN-586 Application Note on the Analog Devices
website at www.analog.com for more information about LVDS.
LVCMOS CLOCK DISTRIBUTION
The AD9575 provides a 33.33 or 62.5 MHz clock output, which
is a dedicated LVCMOS level. Whenever single-ended LVCMOS
clocking is used, some of the following general guidelines
should be followed.
Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
AD9575
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver (see
Figure 21). The value of the resistor is dependent on the board
design and timing requirements (typically 10 Ω to 100 Ω is
used). LVCMOS outputs are limited in terms of the capacitive
load or trace length that they can drive. Typically, trace lengths
less than 6 inches are recommended to preserve signal rise/fall
times and preserve signal integrity.
CMOS
60.4Ω
10Ω ^{1.0 INCH}
MICROSTRIP
5pF
GND
Figure 21. Series Termination of LVCMOS Output
Termination at the far end of the PCB trace is a second option.
The LVCMOS output of the AD9575 does not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 22. The far-end
termination network should match the PCB trace impedance
and provide the desired switching point.
The reduced signal swing may still meet receiver input
requirements in some applications. This can be useful when
driving long trace lengths on less critical nets.
V_PULLUP = 3.3V
10Ω
50Ω
LVCMOS
100Ω
100Ω
3pF
Figure 22. LVCMOS Output with Far-End Termination
TYPICAL APPLICATIONS
AD9575
1 GNDA
0.1µF
1nF
V_S
2 VDDA
SEL0 16
GND 15
V_S
Cx
Cx
3 VDDX LVDS/LVPECL OUT 14
4 XO1
0.1µF
5 XO2
LVDS/LVPECL OUT 13
VDD 12
6 GNDX
VDD_CMOS 11
50Ω
0.1µF
50Ω
V_S
V_S
R_T =
100Ω
7 GNDA CMOS OUT/SEL1 10
0.1µF
V_S
8 VDDA
GND CMOS 9
0.1µF
Figure 23. Typical Application (in LVDS configuration)
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