AD9923A Datasheet, PDF (78/88 Pages) Analog Devices – CCD Signal Processor with V-Driver and Precision Timing™ Generator

AD9923A
Table 52. Memory Configuration Registers
Address Data Default
(Hex) Bits Value Update Name
90
[4:0] 0
VD
VPAT_NUM
91
[4:0] 0
VD
VSEQ_NUM
Description
Total number of V-pattern groups.
Total number of V-sequences.
Table 53. Standby Polarity, Shutter Mux, and FG_TRIG Registers
Address Data Default
(Hex) Bits Value Update Name
Description
E2
[24:0] 0
SCK
STANDBY3POL
Programmable polarities for vertical and shutter outputs during Standby 3.
[0] = XV1 polarity.
[1] = XV2 polarity.
[2] = XV3 polarity.
[3] = XV4 polarity.
[4] = XV5 polarity.
[5] = XV6 polarity.
[6] = XV7 polarity.
[7] = XV8 polarity.
[8] = XV9 polarity.
[9] = XV10 polarity.
[10] = XV11 polarity.
[11] = XV12 polarity.
[12] = XV13 polarity.
[13] = VSG1 polarity.
[14] = VSG2 polarity.
[15] = VSG3 polarity.
[16] = VSG4 polarity.
[17] = VSG5 polarity.
[18] = VSG6 polarity.
[19] = VSG7 polarity.
[20] = VSG8 polarity.
[21] = XSUBCK polarity.
[22] = VSUB polarity.
Note: controls polarity for Standby 1, Standby 2, Standby 3, or if
OUTCONTROL = low.
[23] = MSHUT polarity.
Note: controls polarity for Standby 1, Standby 2, Standby 3, or if
OUTCONTROL = low.
[24] = STROBE polarity.
Note: controls polarity for Standby 1, Standby 2, Standby 3, or if
OUTCONTROL = low.
E6
[0]
0
SCK
VCNT_RUN
0: counters behave the same as AD9923 in sweep region.
1: enables additional toggles after last repeat of sweep region.
EA
[9:0] 0
SCK
TEST3
Required start-up register; must be set to 0x60
EB
[11:0] 300
SCK
TEST4
Test register.
[12] 0
SCK
VSUB0_MUX
0: use VSUB0, 1: Use SHUT0 ^ VSUB0.
[13] 0
SCK
VSUB1_MUX
0: use VSUB1, 1: Use SHUT0 ^ VSUB1.
[14] 0
SCK
TEST5
Test register. Set to 0.
[15] 0
SCK
SHUT1_SHUT2_MUX 0: use SHUT0 ^ SHUT1.
1: Use SHUT0 ^ SHUT2.
F1
[3:0] 0
SCK
FG_TRIGEN
FG_TRIG operation enable and field count selection.
[2:0] Selects field count for pulse (based on mode field counter).
[3] = 1 to enable FG_TRIG signal output.
Rev. 0 | Page 78 of 88