AD9923A Datasheet, PDF (1/88 Pages) Analog Devices – CCD Signal Processor with V-Driver and Precision Timing™ Generator

CCD Signal Processor with V-Driver and
Precision Timing™ Generator
AD9923A
FEATURES
Integrated 15-channel V-driver
12-bit, 36 MHz analog-to-digital converter (ADC)
Similar register map to the AD9923
5-field, 10-phase vertical clock support
Complete on-chip timing generator
Precision Timing core with <600 ps resolution
Correlated double sampler (CDS)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
Black level clamp with variable level control
On-chip 3 V horizontal and RG drivers
2-phase and 4-phase H-clock modes
Electronic and mechanical shutter support
On-chip driver for external crystal
On-chip sync generator with external sync input
8 mm × 8 mm CSP_BGA package with 0.65 mm pitch
APPLICATIONS
Digital still cameras
.
GENERAL DESCRIPTION
The AD9923A is a complete 36 MHz front-end solution for
digital still cameras and other CCD imaging applications.
Similar to the AD9923 product, the AD9923A includes the
analog front end (AFE), a fully programmable timing generator
(TG), and a 15-channel vertical driver (V-driver). A Precision
Timing core allows adjustment of high speed clocks with
approximately 600 ps resolution at 36 MHz operation.
The on-chip V-driver supports up to 15 channels for use with
5-field, 10-phase CCDs.
The analog front end includes black level clamping, CDS, VGA,
and a 12-bit ADC. The timing generator and V-driver provide
all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor
gate pulses, substrate clock, and substrate bias control. The
internal registers are programmed using a 3-wire serial
interface.
Packaged in an 8 mm × 8 mm CSP_BGA, the AD9923A is
specified over an operating temperature range of −25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
–3dB, 0dB, +3dB, +6dB +6dB TO +42dB
CCDIN
CDS
VGA
VREF
AD9923A
12-BIT
12
ADC
RG
HL
H1 TO H4
V1, V2, V3,
V4, V5A, V5B,
V6, V7A, V7B,
V8, V9, V10,
V11, V12, V13
HORIZONTAL
DRIVERS
4
15 _V-DRIVER
13
XV1 TO
XV13 _VERTICAL
8
TIMING
CONTROL
XSG1 TO
XSG8
2
XSUBCK,
XSUBCNT
3
INTERNAL CLOCKS
CLAMP
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
SUBCK
VSUB, MSHUT,
HD
STROBE
VD
SYNC CLI
CLO
Figure 1.
D0 TO D11
DCLK
SL
SDI
SCK
Rev. 0
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