AD9923A Datasheet, PDF (73/88 Pages) Analog Devices – CCD Signal Processor with V-Driver and Precision Timing™ Generator

AD9923A
Address
(Hex)
37
38
Data
Bits
[7:4]
[11:8]
[15:12]
[19:16]
[23:20]
[5:0]
[13:8]
[5:0]
[7:6]
[8]
Default
Value
1
1
1
1
1
24
0
0
0
0
[10:9] 2
[11] 0
Update
Type
SCK
SCK
Name
H2DRV
H3DRV
H4DRV
HLDRV
RGDRV
SHPLOC
SHDLOC
DOUTPHASE
Unused
DCLKMODE
DOUTDELAY
DCLKINV
Description
H2 drive strength.
H3 drive strength.
H4 drive strength.
HL drive strength.
RG drive strength.
SHP sample location.
SHD sample location.
DOUT (internal signal) phase control.
Must be set to 0.
DCLK mode.,
0: DCLK tracks DOUT phase.
1: DCLK phase is fixed.
Data output delay (tOD) with respect to DCLK rising edge.
0: no delay.
1: ~4 ns.
2: ~8 ns.
3: ~12 ns.
Invert DCLK output.
0: no inversion.
1: inversion of DCLK.
Table 49. CLPOB and PBLK Masking Registers
Address
(Hex)
Data
Bits
Default Value
Update
Type
40
[11:0]
FFF
VD
[12]
0
[24:13] FFF
41
[11:0]
FFF
VD
[12]
0
[24:13] FFF
42
[11:0]
FFF
VD
[12]
0
[24:13] FFF
43
[11:0]
FFF
VD
[12]
0
[24:13] FFF
44
[11:0]
FFF
VD
[12]
0
[24:13] FFF
45
[11:0]
FFF
VD
[12]
0
[24:13] FFF
Name
CLPOBMASKSTART1
Unused
CLPOBMASKEND1
CLPOBMASKSTART2
Unused
CLPOBMASKEND2
CLPOBMASKSTART3
Unused
CLPOBMASKEND3
PBLKMASKSTART1
Unused
PBLKMASKEND1
PBLKMASKSTART12
Unused
PBLKMASKEND2
PBLKMASKSTART3
Unused
PBLKMASKEND3
Description
CLPOB Masking Start Line 1.
Must be set to 0.
CLPOB Masking End Line 1.
CLPOB Masking Start Line 2.
Must be set to 0.
CLPOB Masking End Line 2.
CLPOB Masking Start Line 3.
Must be set to 0.
CLPOB Masking End Line 3.
PBLK Masking Start Line 1.
Must be set to 0.
PBLK Masking End Line 1.
PBLK Masking Start Line 2.
Must be set to 0.
PBLK Masking End Line 2.
PBLK Masking Start Line 3.
Must be set to 0.
PBLK Masking End Line 3.
Rev. 0 | Page 73 of 88