AD9517-0BCPZ Datasheet, PDF (76/80 Pages) Analog Devices – 12-Output Clock Generator with Integrated 2.8 GHz VCO

AD9517-0
APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9517
The AD9517 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9517, keep in mind the following
guidelines.
The AD9517 has the following four frequency dividers: the
reference (or R) divider, the feedback (or N) divider, the VCO
divider, and the channel divider. When trying to achieve a
particularly difficult frequency divide ratio requiring a large
amount of frequency division, some of the frequency division
can be done by either the VCO divider or the channel divider,
thus allowing a higher phase detector frequency and more
flexibility in choosing the loop bandwidth.
Within the AD9517 family, lower VCO frequencies generally
result in slightly lower jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.45 GHz to 2.95 GHz) of the AD9517 family. If the desired
frequency plan can be achieved with a version of the AD9517
that has a lower VCO frequency, choosing the lower frequency
part results in the lowest phase noise and the lowest jitter.
However, choosing a higher VCO frequency may result in more
flexibility in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current, and thus allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. It is a very accurate tool
for determining the optimal loop filter for a given application.
USING THE AD9517 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
Data Sheet
on the sampling clock. Considering an ideal ADC of infinite
resolution where the step size and quantization error can be
ignored, the available SNR can be expressed approximately by
SNR(dB)
= 20× log_{}
1
2πf _At _J


where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 70 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
110
1
18
100
SNR = 20log _2πfAtJ
16
90
80
2^tJ_00=fS^100fS
14
70
400_fS
12
1ps
60
2ps
10
50
40
30
10
10ps
8
6
100
1k
f_A (MHz)
Figure 70. SNR and ENOB vs. Analog Input Frequency
See the AN-756 Application Note, Sampled Systems and the Effects
of Clock Phase Noise and Jitter; and the AN-501 Application Note,
Aperture Uncertainty and ADC System Performance, at
www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
may result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can provide
superior clock performance in a noisy environment.) The AD9517
features both LVPECL and LVDS outputs that provide differential
clock outputs, which enable clock solutions that maximize
converter SNR performance. The input requirements of the ADC
(differential or single-ended, logic level, termination) should be
considered when selecting the best clocking/converter solution.
Rev. E | Page 76 of 80