AD9517-0BCPZ Datasheet, PDF (18/80 Pages) Analog Devices – 12-Output Clock Generator with Integrated 2.8 GHz VCO

AD9517-0
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
REFMON 1
LD 2
VCP 3
CP 4
STATUS 5
REF_SEL 6
SYNC 7
LF 8
9
VS 10
CLK 11
CLK 12
PIN 1
INDICATOR
AD9517-0
TOP VIEW
(Not to Scale)
36 VS
35 OUT4 (OUT4A)
34 OUT4 (OUT4B)
33 OUT5 (OUT5A)
32 OUT5 (OUT5B)
31 VS
30 VS
29 OUT7 (OUT7B)
28 OUT7 (OUT7A)
27 OUT6 (OUT6B)
26 OUT6 (OUT6A)
25 VS
NOTES
1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 6. Pin Configuration
Table 20. Pin Function Descriptions
Pin No.
Input/
Output Pin Type
Mnemonic
1
O
3.3 V CMOS REFMON
2
O
3.3 V CMOS LD
3
I
Power
VCP
4
O
3.3 V CMOS CP
5
O
3.3 V CMOS STATUS
6
I
3.3 V CMOS REF_SEL
7
I
3.3 V CMOS SYNC
8
I
Loop filter LF
9
O
10, 24, 25, I
30, 31, 36,
37, 43, 45
11
I
12
I
13
I
14
I
Loop filter BYPASS
Power
VS
Differential
clock input
Differential
clock input
3.3 V CMOS
3.3 V CMOS
CLK
CLK
SCLK
CS
Description
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01A.
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.0 V. This pin is usually 3.3 V for
most applications; but if a 5 V external VCXO is used, this pin should be 5 V.
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
Loop Filter (Input). Connects to VCO control voltage node internally. This pin has
31 pF of internal capacitance to ground, which may influence the loop filter design
for large loop bandwidths.
This pin is for bypassing the LDO to ground with a capacitor.
3.3 V Power Pins.
Along with CLK, this is the self-biased differential input for the clock distribution
section. This pin can be left floating if internal VCO is used.
Along with CLK, this is the self-biased differential input for the clock distribution
section. This pin can be left floating if internal VCO is used.
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select; Active Low.
This pin has an internal 30 kΩ pull-up resistor.
Rev. E | Page 18 of 80