AD9517-0BCPZ Datasheet, PDF (5/80 Pages) Analog Devices – 12-Output Clock Generator with Integrated 2.8 GHz VCO

Data Sheet
AD9517-0
Parameter
Min
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. CPV
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
At 500 kHz PFD Frequency
At 1 MHz PFD Frequency
At 10 MHz PFD Frequency
At 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
PLL DIGITAL LOCK DETECT WINDOW²
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
To Unlock After Lock (Hysteresis)²
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Typ Max
4.8
0.60
2.5
2.7/10
1
2
1.5
2
300
600
900
200
1000
2400
3000
3000
300
Off
330
440
550
660
770
880
990
−165
−162
−151
−143
−220
3.5
7.5
3.5
7
15
11
Unit Test Conditions/Comments
CPV is CP pin voltage; VCP is charge pump power supply voltage
Programmable
mA
With CPRSET = 5.1 kΩ
mA
%
CPV = VCP/2 V
kΩ
nA
%
0.5 < CPV < VCP − 0.5 V
%
0.5 < CPV < VCP − 0.5 V
%
CPV = VCP/2 V
See the VCXO/VCO Feedback Divider N—P, A, B, R section
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz A, B counter input frequency (prescaler input frequency
divided by P)
Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 54
ps
ps
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
The PLL in-band phase noise floor is estimated by measuring
the in-band phase noise at the output of the VCO and
subtracting 20 log(N) (where N is the value of the N divider)
Reference slew rate > 0.25 V/ns; FOM + 10 log(fPFD) is an approxi-
mation of the PFD/CP in-band phase noise (in the flat region)
inside the PLL loop bandwidth; when running closed-loop, the
phase noise, as observed at the VCO output, is increased by
20 log(N)
Signal available at LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
ns
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
ns
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
ns
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
1 _{REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.}
2 _{For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.}
Rev. E | Page 5 of 80