AD9516-1_15 Datasheet, PDF (75/80 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.5 GHz VCO

Data Sheet
AD9516-1
Reg.
Addr.
(Hex) Bits
0x19C 5
Name
Bypass Divider 3.2
4
Bypass Divider 3.1
3
Divider 3 nosync
2
Divider 3 force high
1
Start High Divider 3.2
0
Start High Divider 3.1
0x19D 0
Divider 3 DCCOFF
0x19E [7:4] Low Cycles Divider 4.1
[3:0] High Cycles Divider 4.1
0x19F [7:4]
[3:0]
0x1A0 [7:4]
Phase Offset Divider 4.2
Phase Offset Divider 4.1
Low Cycles Divider 4.2
[3:0] High Cycles Divider 4.2
0x1A1 5
Bypass Divider 4.2
4
Bypass Divider 4.1
3
Divider 4 nosync
2
Divider 4 force high
1
Start High Divider 4.2
0
Start High Divider 4.1
0x1A2 0
Divider 4 DCCOFF
Description
Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.
0: does not bypass (default).
1: bypasses.
Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.
0: does not bypass 3.1 divider logic (default).
1: bypasses 3.1 divider logic.
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Force Divider 3 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
Divider 3.2 starts high/low.
0: starts low (default).
1: starts high.
Divider 3.1 starts high/low.
0: starts low (default).
1: starts high.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses (and powers down) 4.2 divider logic; route clock to 4.2 output.
0: does not bypass 4.2 divider logic (default).
1: bypasses 4.2 divider logic.
Bypasses (and powers down) 4.1 divider logic; route clock to 4.1 output.
0: does not bypass 4.1 divider logic (default).
1: bypasses 4.1 divider logic.
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces Divider 4 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
Divider 4.2 starts high/low.
0: starts low (default).
1: starts high.
Divider 4.1 starts high/low.
0: starts low (default).
1: starts high.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Rev. C | Page 75 of 80