AD9516-1_15 Datasheet, PDF (4/80 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.5 GHz VCO

AD9516-1
Data Sheet
SPECIFICATIONS
Typical is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_LVPECL
VCP
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
Min Typ
3.135 3.3
2.375
VS
4.12
2.7
5.1
Max Unit
3.465 V
VS
V
5.25 V
kΩ
10
kΩ
220
nF
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA);
actual current can be calculated by: CP_lsb = 3.06/CPRSET;
connect to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Frequency Pushing (Open-Loop)
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Input Capacitance
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
Min Typ Max Unit Test Conditions/Comments
2300
0.5
50
1
−105
−124
2650
VCP −
0.5
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
See Figure 15
See Figure 10
VCP ≤ VS when using internal VCO; outside of this range, the CP
spurs may increase due to CP up/down mismatch
f = 2475 MHz
f = 2475 MHz
0
250
1.35 1.60
1.30 1.50
4.0
4.8
4.4
5.3
20
0
0.8
2.0
−100
2
250
1.75
1.60
5.9
6.4
250
250
0.8
+100
MHz
mV p-p
V
V
kΩ
kΩ
MHz
MHz
V p-p
V
V
µA
pF
Differential mode (can accommodate single-ended input by ac
grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match VCM (self-bias voltage)
PLL figure of merit (FOM) increases with increasing slew rate;
see Figure 14
Self-bias voltage of REFIN¹
Self-bias voltage of REFIN¹
Self-biased¹
Self-biased¹
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/µs
Slew rate > 50 V/µs; CMOS levels
Should not exceed VS p-p
Each pin, REFIN/REFIN (REF1/REF2)
100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns
45
MHz Antibacklash pulse width = 6.0 ns
1.3
ns
Register 0x017[1:0] = 01b
2.9
ns
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
6.0
ns
Register 0x017[1:0] = 10b
Rev. C | Page 4 of 80