AD9516-1_15 Datasheet, PDF (24/80 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.5 GHz VCO

AD9516-1
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FREQUENCY (Hz)
Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4
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Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO at
2.4576 GHz; PFD = 15.36 MHz; LBW = 55 kHz; LVPECL Output = 122.88 MHz
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Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 2.488 GHz;
PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
Data Sheet
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Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
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OC-48 OBJECTIVE MASK
AD9516
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F_OBJ
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NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
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JITTER FREQUENCY (kHz)
Figure 41. GR-253 Jitter Tolerance Plot
1000
Rev. C | Page 24 of 80