AD9154 Datasheet, PDF (74/124 Pages) Analog Devices – Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter

AD9154
Register 0x084, Bit 5 notifies the user that the DAC PLL calibration
is completed and is valid.
Register 0x084, Bit 1 notifies the user that the PLL has locked.
Register 0x084, Bits[7:6] and Register 0x084, Bit 5 notify the
user that the DAC PLL hit the upper or lower edge of its operating
band, respectively. If either of these bits are high, recalibrate the
DAC PLL by setting Register 0x083, Bit 7 to 0 and then 1.
Data Sheet
DAC PLL IRQ
The DAC PLL lock and lost signals are available as IRQ events.
Use Register 0x01F, Bit 5 and Bit 4 to enable these signals, and
then use Register 0x023, Bit 5 and Bit 4 to read back their
statuses and reset the IRQ signals. See the Interrupt Request
Operation section.
N1 =
DIVIDE BY
1, 2, 4, 8, 16, 32
f_REF
30MHz ^÷2
TO 1GHz ÷4
÷8
÷16
PFD
80MHz
MAX
RETIMER
UP
CHARGE
PUMP
4-BIT
PROGRAMMABLE,
INTEGRATED
LOOP FILTER
C1 C2
C3
R1
DOWN
R3
VCO
LDO
LC VCO
6GHz
TO
12GHz
÷2
0.1mA TO 6.4mA
B COUNTER
MAXIMUM FREQUENCY = 1.6GHz
ALC CAL
FO CAL
CAL CONTROL BITS
÷2
Figure 78. Device Clock PLL Block Diagram
÷2
÷2
÷2
IQ
IQ
IQ
MUX/SELECTABLE BUFFERS
N_MUX = 4, 8, 16
DAC CLOCK
Rev. B | Page 74 of 124