AD9154 Datasheet, PDF (45/124 Pages) Analog Devices – Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter

Data Sheet
AD9154
TRANSPORT LAYER
LANE 0 OCTETS
LANE 3 OCTETS
TRANSPORT LAYER
(QBD)
DELAY
BUFFER 0
F2S_0
DAC 1_I0[15:0]
DAC 2_Q0[15:0]
PCLK_0
SPI CONTROL
LANE 4 OCTETS
LANE 7 OCTETS
DELAY
BUFFER 1
F2S_1
DAC 3_I0[15:0]
DAC 4_Q0[15:0]
PCLK_1
SPI CONTROL
Figure 57. Transport Layer Block Diagram
The transport layer receives the descrambled JESD204B frames
and converts them to DAC samples based on the programmed
JESD204B parameters shown in Table 42. A number of device
parameters are defined in Table 43.
Table 42. JESD204B Transport Layer Parameters
Parameter Description
F
Number of octets per frame per lane: 1, 2, or 4.
K
Number of frames per multiframe.
K = 32 if F = 1, K = 16 or 32 otherwise.
L
Number of lanes per converter device (per link), as
follows.
1, 2, 4, or 8 (single link mode).
1, 2, or 4 (dual link mode).
M
Number of converters per device (per link), as follows.
1, 2, or 4 (single link mode).
1 or 2 (dual link mode).
S
Number of samples per converter, per frame: 1 or 2.
Table 43. JESD204B Device Parameters
Parameter Description
CF
Number of control words per device clock per link.
Not supported, must be 0.
CS
Number of control bits per conversion sample. Not
supported, must be 0.
HD
High density user data format. Used when samples
must be split across lanes. Set to 1 when F = 1,
otherwise 0.
N
Converter resolution = 16.
N Prime (Nʹ) Total number of bits per sample = 16.
Certain combinations of these parameters, called JESD204B
operating modes, are supported by the AD9154. See Table 44
and Table 45 for a list of supported modes, along with their
associated clock relationships.
Rev. B | Page 45 of 124