CN0385 Datasheet, PDF (7/13 Pages) Analog Devices – Devices Connected

Circuit Note
CN-0385
shorter conversion time, and it allows the user to return to
acquisition phase before the end of conversion. Therefore, if the
user runs the ADC at slower throughput, there is have more
time to settle the kickback.
The signal must be settled by the end of the acquisition phase
for an accurate conversion. To maximize the time given for the
signal to settle, the multiplexer switches channels immediately
after the AD4003 begins its conversion phase.
In addition to settling from the multiplexed signal from the
output of the AD8475, the RC noise filter and AD4003 inputs
also need to settle to the voltage kickback that occurs at the
beginning of the acquisition phase. For more information, see
the Analog Dialogue article, Front-End Amplifier and RC Filter
Design for a Precision SAR Analog-to-Digital Converter.
The settling time for the circuit in Figure 7 was simulated in NI
Multisim, as shown in Figure 8. V1 represents the maximum
voltage step expected at either input of the AD4003 (from a
single-ended output of the AD8475). CNV and S1 simulate the
AD4003 switching from the conversion phase (occurring when
V1 changes value) to the acquisition phase (300 ns after start of
conversion). CNV keeps S1 open until 300 ns after V1 steps
from 0 V to 4 V to represent the transition from the conversion
phase to the acquisition phase. ADC_IN is the voltage that is
sampled by the AD4003 on a CNV rising edge.
The settling time for this portion of the system is equal to the
time between V1 switching to 4 V (at TIME = 0, see Figure 9) to
ADC_IN settling to 0.001% of 4 V.
XSC1
G
T
ABC D
R1
V1
200Ω
V1
0V 4V
5µs 10µs
RC_EXT
C1
120pF
S1
+–
R2
400Ω
ADC_IN
C2
40pF
CNV PHASE
0V 3.3V
300ns 10µs
U1
NOT
CNV
Figure 8. Multisim™ Settling Time Model of the AD4003 and RC Noise Filter
The simulation results are shown in Figure 9. The time taken
for the output to settle to 0.001% of 4 V is t = S_AD4003 711 ns.
4.0V
4.0V
3.3V
4.0V
V1
RC_EXT
CNV
ADC_IN
711ns, 4V
TIME (µs)
Figure 9. Settling Time Waveforms for the AD4003 and RC Noise Filter
Simulation Model
Total System Settling Time
The total settling time of the entire circuit shown in Figure 1
can now be estimated by calculating the rss of the settling times
for each component:
• tS_ADG5207 = 188 ns
• tS_AD8251 = 1000 ns
• tS_AD8475 = 200 ns
• tS_AD4003 = 711 ns
• t_{S_TOTAL} = 188 ns² + 1 μs² + 200 ns² + 711 ns² ≈ 1257 ns
The expected maximum channel switching sample rate of the
system is then
f _SR
<
1
1257 ns
≈
795 kSPS
Offset and Gain Error Results
Table 4 shows the offset error measured (in LSBs) for each of the
channels in each gain configuration for the circuit in Figure 1.
Table 4 also shows the average offset error of all of the channels
for each gain configuration.
The offset errors were measured by grounding all of the channel
inputs and collecting and averaging 32,768 samples taken on
each of the channels in each gain configuration.
Table 4. Offset Error Measurements for all Channels and Gain Configurations (Error in LSBs)
Gain Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7
0.4 1.34
1.33
1.31
1.36
1.44
1.45
1.46
0.8 1.98
1.99
2.02
2.06
2.00
1.98
1.99
1.6 3.25
3.19
3.22
3.19
3.17
3.08
3.13
3.2 5.57
5.66
5.67
5.55
5.57
5.50
5.54
Channel 8
1.48
1.97
3.14
5.52
Channel Average
1.40
2.00
3.17
5.57
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