CN0385 Datasheet, PDF (6/13 Pages) Analog Devices – Devices Connected

CN-0385
Circuit Note
Each channel functions similarly to an RC circuit having an
associated time constant that dominates settling time.
Dynamically switching channels complicates signal settling;
at the time channels are switched, the difference between the
previous output and the current input produces a kickback
transient. This kickback is similar to the one that occurs at the
input to the AD4003 as it enters the acquisition phase. For a
more detailed description, see the Analog Dialogue article,
Front-End Amplifier and RC Filter Design for a Precision SAR
Analog-to-Digital Converter.
The circuit in Figure 4 was simulated using NI Multisim™, as
shown in Figure 5, with the following component values from
the respective device data sheets:
 RON = 250 Ω
 CS = 3.5 pF
 CD = 36 pF
 RIN||CIN = 1.25 GΩ||2 pF
The input resistance of the AD8251 (RIN) is sufficiently large
(1.25 GΩ) to be omitted from simulation.
G
T
ABC D
XSC1
Settling Time of the AD8251 and AD8475
The AD8251 data sheet specifies its settling time for a variety of
input voltage step sizes down to a 0.001% error for each gain
configuration. Given a load of 10 kΩ and gain setting of 1, the
AD8251 can settle a 20 V step at its output to 0.001% in
approximately 1 μs. The gain of 1 setting requires the most
settling time; therefore, the settling time analysis uses 1 μs.
However, the 1 μs number may not be accurate when the
AD8251 is driving one of the inputs of the AD8475, which has
an input impedance of 2.92 kΩ instead of 10 kΩ. It is also not
possible to ascertain settling time of the AD8251 to 18-bit
resolution, because of the nonlinear relationship between
settling time and precision. Therefore, the best settling time
estimation is 0.001% error (or 16-bit resolution).
The AD8475 has a settling time specification of 50 ns to 0.001%
for a 2 V differential output step. The maximum voltage step size
expected on the outputs of the AD8475 is twice the reference
voltage (VREF), or approximately 8 V. Assuming that the settling
time is proportional to the output voltage step, the settling time to
0.001% (16 bits) for an 8 V step is approximately 200 ns (4 × 50 ns).
The settling time of each amplifier is, therefore,
 tS_AD8251 = 1 μs
 tS_AD8475 = 200 ns
100Ω
R_ON1
250Ω
S1
V1
+10V
56pF
CS1_OFF
3.5pF
1
2
100Ω
R_ON2
250Ω
1
2
+–
V2
–10V
56pF
CS2_OFF
3.5pF
OUTPUT
CD1
C1
36pF
2pF
Settling Time of the RC Noise Filter and AD4003
Figure 7 shows the equivalent circuit of the inputs of the AD4003.
REXT and CEXT are the components in the RC wideband noise
filter in front of the ADC. RIN and CIN are the input resistance
and capacitance of the AD4003, respectively. CIN is mainly the
internal capacitive digital-to-analog converter (DAC). CPIN is
primarily the pin capacitance, and is ignored. The values for
these components are as follows:
MUX CONTROL
Figure 5. Multisim Settling Time Model of the ADG5207
The simulation results are shown in Figure 6. The time required
for the output of the ADG5207 to settle to 0.001% of 10 V is
tS_ADG5207 = 188 ns.
MUX CTR (V)
4
3
2
 REXT = 200 Ω
 CEXT = 120 pF
 RIN = 400 Ω
 CIN = 40 pF
REF
R_EXT
D1
IN+ OR IN–
EXT
C_PIN
D2
AD4003
R_IN
C_IN
1
188ns, +10V
0
OUTPUT (V)
10
GND
GND
GND
Figure 7. Settling Time Model of the AD4003 and RC Noise Filter
5
The AD4003 employs an internal capacitive DAC and a charge
0
redistribution algorithm to determine its output code. The
0ns, –10V
conversion process contains two phases, acquisition and
–5
conversion. During acquisition, the capacitive DAC is
–10
connected to the input terminals of the AD4003. During
–50
0
50
100
150
200
250
300
TIME (ns)
Figure 6. Settling Time Waveforms for the ADG5207 Simulation Model
conversion, it is disconnected from the input terminals, and
internal logic performs the charge-redistribution algorithm.
Compared to other PulSAR ADCs, the AD4003 has a much
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