AD9887_15 Datasheet, PDF (7/40 Pages) Analog Devices – Dual Interface for Flat Panel Displays

AD9887
Table I. Complete Pinout List
Pin
Type
Pin
Name
Function
Value
Pin
Number Interface
Analog Video
Inputs
External
Sync/Clock
Inputs
Sync Outputs
Voltage
Reference
Clamp Voltages
PLL Filter
Power Supply
Serial Port
(2-Wire
Serial Interface)
Data Outputs
Data Clock
Outputs
Sync Detect
Scan Function
No Connect
R_AIN
G_AIN
B_AIN
Analog Input for Converter R
Analog Input for Converter G
Analog Input for Converter B
0.0 V to 1.0 V 119
0.0 V to 1.0 V 110
0.0 V to 1.0 V 100
HSYNC
Horizontal SYNC Input
3.3 V CMOS 82
VSYNC
Vertical SYNC Input
3.3 V CMOS 81
SOGIN
Input for Sync-on-Green
0.0 V to 1.0 V 108
CLAMP
Clamp Input (External CLAMP Signal)
3.3 V CMOS 93
COAST
PLL COAST Signal Input
3.3 V CMOS 84
CKEXT
External Pixel Clock Input (to Bypass the PLL) to V_DD or Ground 3.3 V CMOS
83
CKINV
HSOUT
VSOUT
SOGOUT
REFOUT
E ^REFIN
R_MIDSCV
R_CLAMPV
G_MIDSCV
T _GCLAMPV
B_MIDSCV
B_CLAMPV
FILT
E _VD
V_DD
PV_D
L GND
SDA
SCL
A0
A1
O _{Red B[7:0]}
Green B[7:0]
Blue B[7:0]
Red A[7:0]
S _{Green A[7:0]}
Blue A[7:0]
DATACK
DATACK
B _SCDT
SCAN_IN
SCAN_OUT
O^SCANCLK
ADC Sampling Clock Invert
HSYNC Output Clock (Phase-Aligned with DATACK)
VSYNC Output Clock (Phase-Aligned with DATACK)
Sync on Green Slicer Output
Internal Reference Output (Bypass with 0.1 µF to Ground)
Reference Input (1.25 V ± 10%)
Red Channel Midscale Clamp Voltage Output
Red Channel Midscale Clamp Voltage Input
Green Channel Midscale Clamp Voltage Output
Green Channel Midscale Clamp Voltage Input
Blue Channel Midscale Clamp Voltage Output
Blue Channel Midscale Clamp Voltage Input
Connection for External Filter Components for Internal PLL
Analog Power Supply
Output Power Supply
PLL Power Supply
Ground
Serial Port Data I/O
Serial Port Data Clock (100 kHz Max)
Serial Port Address Input 1
Serial Port Address Input 2
Port B/Odd Outputs of Converter “Red,” Bit 7 Is the MSB
Port B/Odd Outputs of Converter “Green,” Bit 7 Is the MSB
Port B/Odd Outputs of Converter “Blue,” Bit 7 Is the MSB
Port A/Even Outputs of Converter “Red,” Bit 7 Is the MSB
Port A/Even Outputs of Converter “Green,” Bit 7 Is the MSB
Port A/Even Outputs of Converter “Blue,” Bit 7 Is the MSB
Data Output Clock for the Analog and Digital Interface
Data Output Clock Complement for the Analog Interface Only
Sync Detect Output
Input for SCAN Function
Output for SCAN Function
Clock for SCAN Function
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
1.25 V
1.25 V ± 10%
0.0 V to 0.75 V
0.0 V to 0.75 V
0.0 V to 0.75 V
3.3 V ± 10%
3.3 V ± 10%
3.3 V ± 10%
0V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
94
139
138
140
126
125
120
118
111
109
101
99
78
92
91
90
89
153–160
13–20
33–40
143–150
3–10
23–30
134
135
136
129
45
50
NC
These Pins Should be Left Unconnected
71–73
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Both
Both
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Digital Video
Data Inputs
Digital Video
Clock Inputs
Data Enable
R_x0+
R_x0–
R_x1+
R_x1–
R_x2+
R_x2–
R_xc+
R_xc–
DE
Digital Input Channel 0 True
Digital Input Channel 0 Complement
Digital Input Channel 1 True
Digital Input Channel 1 Complement
Digital Input Channel 2 True
Digital Input Channel 2 Complement
Digital Data Clock True
Digital Data Clock Complement
Data Enable
62
63
59
60
56
57
65
66
3.3 V CMOS 137
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Control Bits
CTL[0:3]
Decoded Control Bits
3.3 V CMOS 46–49 Digital
R_TERM
R_TERM
Sets Internal Termination Resistance
53
Digital
REV. 0
–7–