AD9887_15 Datasheet, PDF (1/40 Pages) Analog Devices – Dual Interface for Flat Panel Displays

a
Dual Interface for
Flat Panel Displays
AD9887
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Analog Interface
140 MSPS Maximum Conversion Rate
330 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
REFIN
ANALOG
INTERFACE
REF
REFOUT
500 ps p-p PLL Clock Jitter at 140 MSPS
8
R_OUTA
3.3 V Power Supply
Full Sync Processing
Midscale Clamp
4:2:2 Output Format Mode
Digital (DVI 1.0 Compatible) Interface
112 MHz Operation (1 Pixel/Clock Mode)
High Skew Tolerance of One Full Input Clock
E _{Sync Detect for “Hot Plugging”}
APPLICATIONS
RGB Graphics Processing
T LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Micro Displays
E ^{Digital TV}
GENERAL DESCRIPTION
L _{The AD9887 offers designers the flexibility of a dual analog and}
digital interface for flat panel displays (FPDs) on a single chip.
Both interfaces are optimized for excellent image quality supporting
display resolutions up to SXGA (1280 × 1024 at 75 Hz). Either the
analog or the digital interface can be selected by the user.
O _{Analog Interface}
For ease of design and to minimize cost, the AD9887 is a fully
integrated interface solution for FPDs. The AD9887 includes an
S ^{analog interface with a 140 MHz triple ADC with internal 1.25 V}
reference, PLL to generate a pixel clock from HSYNC, program-
mable gain, offset, and clamp control. The user provides only a
3.3 V power supply, analog input, and HSYNC. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
B _{The AD9887’s on-chip PLL generates a pixel clock from HSYNC.}
Pixel clock output frequencies range from 12 MHz to 140 MHz.
PLL clock jitter is 500 ps p-p typical at 140 MSPS. When a
O ^{COAST signal is presented, the PLL maintains its output fre-}
R_AIN
G_AIN
B_AIN
HSYNC
VSYNC
COAST
CLAMP
CKINV
CKEXT
FILT
SCL
SDA
A₁
A₀
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
R_TERM
CLAMP
8
A/D
8
R_OUTB
CLAMP
8
A/D
8
G_OUTA
8
G_OUTB
CLAMP
8
A/D
8
B_OUTA
8
B_OUTB
SYNC
PROCESSING
AND CLOCK
GENERATION
2
DATACK
HSOUT
VSOUT
SOGOUT
S_CDT
M
U
X
SERIAL REGISTER
E
AND
S
POWER MANAGEMENT
DIGITAL
INTERFACE
DVI
RECEIVER
8
8
8
2
8 ^ROUTA
8 ^ROUTB
8 ^GOUTA
8 ^GOUTB
8 ^BOUTA
8 ^BOUTB
DATACK
DE
HSYNC
VSYNC
AD9887
8
8
8
8
8
8
2
R_OUTA
R_OUTB
G_OUTA
G_OUTB
B_OUTA
B_OUTB
DATACK
HSOUT
VSOUT
SOGOUT
DE
quency in the absence of HSYNC. A sampling phase adjustment is
provided. Data, HSYNC and Clock output phase relationships are
maintained. The PLL can be disabled and an external clock input
provided as the pixel clock. The AD9887 also offers full sync pro-
cessing for composite sync and sync-on-green applications.
Digital Interface
The AD9887 contains a Digital Video Interface (DVI 1.0) compat-
ible receiver. This receiver supports displays ranging from VGA
to SXGA (25 MHz to 112 MHz). The receiver operates with
true color (24-bit) panels in 1 or 2 pixel(s)/clock mode, and also
A clamp signal is generated internally or may be provided by _{features an intrapair skew tolerance up to one full clock cycle.}
the user through the CLAMP input pin. The analog interface
is fully programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9887 is pro-
vided in a 160-lead MQFP surface mount plastic package and is
specified over the 0°C to 70°C temperature range.
REV. 0
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under any patent or patent rights of Analog Devices.
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© Analog Devices, Inc., 2001