AD9887_15 Datasheet, PDF (22/40 Pages) Analog Devices – Dual Interface for Flat Panel Displays

AD9887
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PXCK
HS
ADCCK
6-PIPE DELAY
DATACK
GOUTA
Y0
Y1 Y2
Y3
Y4 Y5
Y6
ROUTA
HSOUT
U0
V0 U2
V2
U4 V4
U6
V6
Figure 27. 4:2:2 Output Mode
TE _{Pin Type}
Digital Video Data Inputs
LE _{Digital Video Clock Inputs}
Termination Control
O ^Outputs
OBS ^{Power Supply}
Table VIII. Digital Interface Pin List
Pin Name Function
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
R_TERM
DE
HSYNC
VSYNC
CTL0, CTL1,
CTL2, CTL3
V_D
PV_D
V_DD
GND
GND
Digital Input Channel 0 True
Digital Input Channel 0 Complement
Digital Input Channel 1 True
Digital Input Channel 1 Complement
Digital Input Channel 2 True
Digital Input Channel Two’s Complement
Digital Data Clock True
Digital Data Clock Complement
Control Pin for Setting the Internal
Termination Resistance
Data Enable
HSYNC Output
VSYNC Output
Decoded Control Bit Outputs
Main Power Supply
PLL Power Supply
Output Power Supply
Ground Supply
Ground Supply
Value
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V ± 5%
3.3 V ± 5%
3.3 V or 2.5 V ± 5%
0V
0V
Pin No.
62
63
59
60
56
57
65
66
53
137
139
138
46–49
–22–
REV. 0