AD9577 Datasheet, PDF(7/44 Page) Analog Devices – Clock Generator with Dual PLLs

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

AD9577 Datasheet, PDF (7/44 Pages) Analog Devices – Clock Generator with Dual PLLs

◁

Data Sheet

AD9577

PLL2 INTEGER-N MODE CHARACTERISTICS

Table 4. Bleed = 0

Parameter

NOISE CHARACTERISTICS

Phase Noise (106.25 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (156.25 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (625 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (106.25 MHz LVDS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (156.25 MHz LVDS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (625 MHz LVDS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (106.25 MHz CMOS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Min Typ Max

â116

â123

â127

â148

â156

â158

â113

â120

â124

â146

â156

â101

â108

â112

â134

â149

â150

â117

â123

â127

â147

â156

â113

â120

â124

â145

â155

â101

â108

â112

â133

â148

â149

â117

â123

â127

â147

â156

â157

Unit

dBc/Hz

Test Conditions/Comments1

Nb = 102, Vx = 4, Dx = 6, fPFD = 25 MHz

Nb = 100, Vx = 4, Dx = 4, fPFD = 25 MHz

Nb = 100, Vx = 2, Dx = 2, fPFD = 25 MHz

Nb = 102, Vx = 4, Dx = 6, fPFD = 25 MHz

Nb = 100, Vx = 4, Dx = 4, fPFD = 25 MHz

Nb = 100, Vx = 2, Dx = 2, fPFD = 25 MHz

Nb = 102, Vx = 4, Dx = 6, fPFD = 25 MHz

Rev. 0 | Page 7 of 44

▷