AD9577 Datasheet, PDF (38/44 Pages) Analog Devices – Clock Generator with Dual PLLs

AD9577
I²C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
SLAVE ADDRESS [6:0]
R/W
CTRL
10 0 0 0 00 X
0 = WR
1 = RD
Figure 44. Slave Address Configuration
Data Sheet
S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S)
Figure 45. I²C Write Data Transfer
DATA A(S) P
S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M)
DATA A(M) P
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
P = STOP BIT
A(M) = LACK OF ACKNOWLEDGE BY MASTER
A(M) = ACKNOWLEDGE BY MASTER
Figure 46. I²C Read Data Transfer
START BIT
SDA
SLAVE ADDRESS
A6
A5
SUB ADDRESS
A7
A0
DATA
D7
D0
STOP BIT
SCL
S
SLADDR[4:0]
WR ACK
SUB ADDR[6:1]
ACK
Figure 47. I²C Data Transfer Timing
DATA[6:1]
t_F
SDA
SCL
S
t_SU;DAT
t_HD;STA
t_R
t_F
t_LOW
t_SU;STO
t_HD;STA
t_HD;DAT
t_{HIGH tSU;STA}
S
Figure 48. I²C Port Timing Diagram
t_BUF
t_R
P
S
ACK
P
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