AD9680 Datasheet, PDF (67/97 Pages) Analog Devices – Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter

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AD9680
Table 24. AD9680 Control Characters used in JESD204B
Abbreviation
/R/
/A/
/Q/
/K/
/F/
Control Symbol
/K28.0/
/K28.3/
/K28.4/
/K28.5/
/K28.7/
8-Bit Value
000 11100
011 11100
100 11100
101 11100
111 11100
10-Bit Value,
RD¹ = −1
001111 0100
001111 0011
001111 0100
001111 1010
001111 1000
1 _{RD means running disparity.}
10-Bit Value,
RD¹ = +1
110000 1011
110000 1100
110000 1101
110000 0101
110000 0111
Description
Start of multiframe
Lane alignment
Start of link configuration data
Group synchronization
Frame alignment
PHYSICAL LAYER (DRIVER) OUTPUTS
Digital Outputs, Timing, and Controls
The AD9680 physical layer consists of drivers that are defined in
the JEDEC Standard JESD204B, July 2011. The differential digital
outputs are powered up by default. The drivers use a dynamic
100 Ω internal termination to reduce unwanted reflections.
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 300 mV p-p swing at the receiver
(see Figure 159). Alternatively, single-ended 50 Ω termination
can be used. When single-ended termination is used, the
termination voltage is DRVDD/2. Otherwise, 0.1 µF ac coupling
capacitors can be used to terminate to any single-ended voltage.
V_RXCM
DRVDD
SERDOUTx+
SERDOUTx–
100Ω
DIFFERENTIAL
0.1µF TRACE PAIR
100Ω
0.1µF
50Ω 50Ω
OR
RECEIVER
OUTPUT SWING = 300mV p-p
V_CM = V_RXCM
Figure 159. AC-Coupled Digital Output Termination Example
The AD9680 digital outputs can interface with custom ASICs
and FPGA receivers, providing superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a single differential 100 Ω termination
resistor placed as close to the receiver inputs as possible. The
common mode of the digital output automatically biases itself
to half the DRVDD supply of 1.2 V (VCM = 0.6 V). See Figure 160
for dc coupling the outputs to the receiver logic.
DRVDD
SERDOUTx+
100Ω
DIFFERENTIAL
TRACE PAIR
100Ω
RECEIVER
SERDOUTx–
If there is no far-end receiver termination, or if there is poor
differential trace routing, timing errors can result. To avoid such
timing errors, it is recommended that the trace length be less
than six inches, and that the differential output traces be close
together and at equal lengths.
Figure 161 to Figure 166 show an example of the digital output
data eye, time interval error (TIE) jitter histogram, and bathtub
curve for one AD9680 lane running at 10 Gbps and 6 Gbps,
respectively. The format of the output data is twos complement
by default. To change the output data format, see the Memory Map
section (Register 0x561 in Table 36).
De-Emphasis
De-emphasis enables the receiver eye diagram mask to be met
in conditions where the interconnect insertion loss does not
meet the JESD204B specification. Use the de-emphasis feature
only when the receiver is unable to recover the clock due to
excessive insertion loss. Under normal conditions, it is disabled
to conserve power. Additionally, enabling and setting too high a
de-emphasis value on a short link can cause the receiver eye
diagram to fail. Use the de-emphasis setting with caution
because it can increase electromagnetic interference (EMI). See
the Memory Map section (Register 0x5C1 to Register 0x5C5 in
Table 36) for more details.
Phase-Locked Loop
The phase-locked loop (PLL) is used to generate the serializer
clock, which operates at the JESD204B lane rate. The status of
the PLL lock can be checked in the PLL locked status bit
(Register 0x56F, Bit 7). This read only bit lets the user know if
the PLL has achieved a lock for the specific setup. The JESD204B
lane rate control, Bit 4 of Register 0x56E, must be set to
correspond with the lane rate.
OUTPUT SWING = 300mV p-p
V_CM = DRVDD/2
Figure 160. DC-Coupled Digital Output Termination Example
Rev. C | Page 67 of 97