AD9680 Datasheet, PDF (1/97 Pages) Analog Devices – Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V, Analog-to-Digital Converter

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Dual, 14-Bit, 1.25 GSPS, 1.2 V/2.5 V,
Analog-to-Digital Converter
AD9680
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
1.65 W total power per channel at 1 GSPS (default settings)
SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz
SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS),
60.5 dBFS at 1 GHz (AIN = −1.0 dBFS)
ENOB = 10.8 bits at 10 MHz
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −154 dBFS/Hz at 1 GSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
No missing codes
Internal ADC voltage reference
Flexible input range: 1.46 V p-p to 1.94 V p-p
AD9680-1250: 1.58 V p-p nominal
AD9680-1000 and AD9680-820: 1.70 V p-p nominal
AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
Programmable termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
2 GHz usable analog input full power bandwidth
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
2 integrated wideband digital processors per channel
12-bit NCO, up to 4 half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD
(1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V)
VIN+A
VIN–A
FD_A
FD_B
VIN+B
VIN–B
V_1P0
CLK+
CLK–
BUFFER
ADC
CORE
14
DDC
SIGNAL
4
MONITOR
14
ADC
CORE
BUFFER
DDC
CONTROL
REGISTERS
FAST
DETECT
CLOCK
GENERATION
SIGNAL
MONITOR
JESD204B
SUBCLASS 1
CONTROL
÷2
SPI CONTROL
÷4
÷8
AD9680
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SYNCINB±
SYSREF±
PDWN/
STBY
AGND DRGND DGND SDIO SCLK CSB
Figure 1.
PRODUCT HIGHLIGHTS
1. Wide full power bandwidth supports IF sampling of signals
up to 2 GHz.
2. Buffered inputs with programmable input termination eases
filter design and implementation.
3. Four integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
4. Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
5. Programmable fast overrange detection.
6. 9 mm × 9 mm, 64-lead LFCSP.
Rev. C
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