ADSP-21367_08 Datasheet, PDF (6/56 Pages) Analog Devices – SHARC Processors

ADSP-21367/ADSP-21368/ADSP-21369
Table 2. Internal Memory Space ¹
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 Bits)
Extended Precision Normal or
Instruction Word (48 Bits)
Normal Word (32 Bits)
Short Word (16 Bits)
Block 0 ROM (Reserved)
0x0004 0000–0x0004 BFFF
Block 0 ROM (Reserved)
0x0008 0000–0x0008 FFFF
Block 0 ROM (Reserved)
0x0008 0000–0x0009 7FFF
Block 0 ROM (Reserved)
0x0010 0000–0x0012 FFFF
Reserved
0x0004 F000–0x0004 FFFF
Reserved
0x0009 4000–0x0009 FFFF
Reserved
0x0009 E000–0x0009 FFFF
Reserved
0x0013 C000–0x0013 FFFF
Block 0 SRAM
0x0004 C000–0x0004 EFFF
Block 0 SRAM
0x0009 0000–0x0009 3FFF
Block 0 SRAM
0x0009 8000–0x0009 DFFF
Block 0 SRAM
0x0013 0000–0x0013 BFFF
Block 1 ROM (Reserved)
0x0005 0000–0x0005 BFFF
Block 1 ROM (Reserved)
0x000A 0000–0x000A FFFF
Block 1 ROM (Reserved)
0x000A 0000–0x000B 7FFF
Block 1 ROM (Reserved)
0x0014 0000–0x0016 FFFF
Reserved
0x0005 F000–0x0005 FFFF
Reserved
0x000B 4000–0x000B FFFF
Reserved
0x000B E000–0x000B FFFF
Reserved
0x0017 C000–0x0017 FFFF
Block 1 SRAM
0x0005 C000–0x0005 EFFF
Block 1 SRAM
0x000B 0000–0x000B 3FFF
Block 1 SRAM
0x000B 8000–0x000B DFFF
Block 1 SRAM
0x0017 0000–0x0017 BFFF
Block 2 SRAM
0x0006 0000–0x0006 0FFF
Block 2 SRAM
0x000C 0000–0x000C 1554
Block 2 SRAM
0x000C 0000–0x000C 1FFF
Block 2 SRAM
0x0018 0000–0x0018 3FFF
Reserved
0x0006 1000– 0x0006 FFFF
Reserved
0x000C 1555–0x000C 3FFF
Reserved
0x000C 2000–0x000D FFFF
Reserved
0x0018 4000–0x001B FFFF
Block 3 SRAM
0x0007 0000–0x0007 0FFF
Block 3 SRAM
0x000E 0000–0x000E 1554
Block 3 SRAM
0x000E 0000–0x000E 1FFF
Block 3 SRAM
0x001C 0000–0x001C 3FFF
Reserved
0x0007 1000–0x0007 FFFF
Reserved
0x000E 1555–0x000F FFFF
Reserved
0x000E 2000–0x000F FFFF
Reserved
0x001C 4000–0x001F FFFF
1 _{The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.}
A set of programmable timing parameters is available to config-
ure the SDRAM banks to support slower memory devices. The
memory banks can be configured as either 32 bits wide for max-
imum performance and bandwidth or 16 bits wide for
minimum device count and lower system cost.
The SDRAM controller address, data, clock, and control pins
can drive loads up to distributed 30 pF load. For larger memory
systems, the SDRAM controller external buffer timing should
be selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
Table 3. External Memory for NonSDRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in
Words
14M
16M
16M
16M
Address Range
0x0020 0000–0x00FF FFFF
0x0400 0000–0x04FF FFFF
0x0800 0000–0x08FF FFFF
0x0C00 0000–0x0CFF FFFF
Table 4. External Memory for SDRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in
Words
62M
64M
64M
64M
Address Range
0x0020 0000–0x03FF FFFF
0x0400 0000–0x07FF FFFF
0x0800 0000–0x0BFF FFFF
0x0C00 0000–0x0FFF FFFF
Asynchronous Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif-
ferent timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, flash, and EPROM,
as well as I/O devices that interface with standard memory con-
trol lines. Bank 0 occupies a 14M word window and Banks 1, 2,
and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of
interfacing to a range of memories and I/O devices tailored
either to high performance or to low cost and power.
Rev. C | Page 6 of 56 | January 2008