ADSP-21367_08 Datasheet, PDF (1/56 Pages) Analog Devices – SHARC Processors

SHARC Processors
ADSP-21367/ADSP-21368/ADSP-21369
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bits of on-chip SRAM and 6M bits of
on-chip mask programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital audio interface, S/PDIF
transceiver, serial ports, 8-channel asynchronous sample
rate converter, precision clock generators, and more. For
complete ordering information, see Ordering Guide on
Page 55.
CORE PROCESSOR
TIMERS
INSTRUCTION
CACHE
32u 48-BIT
DAG1
8 u 4 u 32
DAG2
8 u 4 u 32
PROGRAM
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
32
32
PM DATA BUS ⁶⁴
DM DATA BUS ⁶⁴
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
PX REGISTER
4 BLOCKS OF
ON-CHIP MEMORY
2M BIT RAM
6M BIT ROM
ADDR
DATA
IOA(24)
IOD(32)
JTAG TEST & EMULATION
FLAGS4-15
PWM
EXTERNAL PORT
SDRAM
7
CONTROLLER
3
ASYNCHRONOUS
MEMORY INTERFACE
8
SHARED MEMORY
INTERFACE
32
DATA
18
CONTROL
24
ADDRESS
IOP REGISTER (MEMORY MAPPED)
CONTROL, STATUS, AND DATA BUFFERS
DMA
CONTROLLER
34 CHANNELS
MEMORY-TO-
MEMORY DMA (2)
4 _{GPIO FLAGS/}
IRQ/TIMEXP
S
PRECISION CLOCK
GENERATORS (4)
SRC (8 CHANNELS)
SPDIF (Rx/Tx)
SERIAL PORTS (8)
INPUT DATA PORT/
PDAP
DAI PINS
DIGITAL AUDIO INTERFACE
20
Figure 1. Functional Block Diagram
SPI PORT (2)
2-WIRE
INTERFACE
DPI PINS
UART (2)
TIMERS (3)
DIGITAL PERIPHERAL INTERFACE
I/O PROCESSOR
14
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Rev. C
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