AD7194 Datasheet, PDF (6/56 Pages) Analog Devices – 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA

AD7194
Parameter
Min
Typ
SYSTEM CALIBRATION²
Full-Scale Calibration Limit
Zero-Scale Calibration
Limit
−1.05 × FS
Input Span
0.8 × FS
POWER REQUIREMENTS⁷
Power Supply Voltage
AVDD − AGND
3
DVDD − DGND
2.7
Power Supply Currents
AIDD Current
0.85
1
2.8
3.2
3.8
4.3
DIDD Current
0.35
0.5
1.5
IDD
Max
1.05 × FS
2.1 × FS
5.25
5.25
1.1
1.35
3.6
3.85
4.7
5.3
0.4
0.6
3
Unit
Test Conditions/Comments¹
V
V
V
V
V
mA
Gain = 1, buffer off
mA
Gain = 1, buffer on
mA
Gain = 8, buffer off
mA
Gain = 8, buffer on
mA
Gain = 16 to 128, buffer off
mA
Gain = 16 to 128, buffer on
mA
DVDD = 3 V
mA
DVDD = 5 V
mA
External crystal used
μA
Power-down mode
1 _{Temperature range: −40°C to +105°C.}
2 _{Specification is not production tested, but is supported by characterization data at initial product release.}
3 _{FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.}
4 _{Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system}
full-scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5 _{The analog inputs are configured for differential mode.}
6 _{REJ60 is a bit in the mode register. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous}
50 Hz/60 Hz rejection.
7 _{Digital inputs equal to DVDD or DGND.}
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