AD7194 Datasheet, PDF (35/56 Pages) Analog Devices – 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA

Continuous Read
Rather than write to the communications register each time a
conversion is complete to access the data, the AD7194 can be
configured so that the conversions are placed on the DOUT/
RDY line automatically. By writing 01011100 to the communi-
cations register, the user need only apply the appropriate number
of SCLK cycles to the ADC, and the conversion word is auto-
matically placed on the DOUT/RDY line when a conversion is
complete. The ADC should be configured for continuous
conversion mode.
When DOUT/RDY goes low to indicate the end of a conversion,
sufficient SCLK cycles must be applied to the ADC; the data
conversion is then placed on the DOUT/RDY line. When the
conversion is read, DOUT/RDY returns high until the next
conversion is available. In this mode, the data can be read only
once. The user must also ensure that the data-word is read
CS
AD7194
before the next conversion is complete. If the user has not read
the conversion before the completion of the next conversion,
or if insufficient serial clocks are applied to the AD7194 to
read the word, the serial output register is reset when the next
conversion is complete, and the new conversion is placed in the
output serial register.
To exit the continuous read mode, Instruction 01011000 must
be written to the communications register while the RDY pin is
low. While in the continuous read mode, the ADC monitors
activity on the DIN line so that it can receive the instruction to
exit the continuous read mode. Additionally, a reset occurs if 40
consecutive 1s are seen on DIN. Therefore, DIN should be held
low in continuous read mode until an instruction is to be written to
the device.
DIN
DOUT/RDY
SCLK
0x5C
DATA
Figure 26. Continuous Read
DATA
DATA
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