AD7194 Datasheet, PDF (1/56 Pages) Analog Devices – 8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA

8-Channel, 4.8 kHz, Ultralow Noise,
24-Bit Sigma-Delta ADC with PGA
AD7194
FEATURES
Pressure measurement
Fast settling filter option
8 differential/16 pseudo differential input channels
RMS noise: 11 nV at 4.7 Hz (gain = 128)
15.5 noise-free bits at 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Temperature measurement
Flow measurement
Weigh scales
Chromatography
Medical and scientific instrumentation
Offset drift: ±5 nV/°C
Gain drift: ±1 ppm/°C
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply
AVDD: 3 V to 5.25 V
DVDD: 2.7 V to 5.25 V
Current: 4.65 mA
Temperature range: −40°C to +105°C
GENERAL DESCRIPTION
The AD7194 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can interface directly to the ADC.
The device can be configured to have eight differential inputs or
sixteen pseudo differential inputs. The on-chip 4.92 MHz clock
can be used as the clock source to the ADC or, alternatively, an
external clock or crystal can be used. The output data rate from
the part can be varied from 4.7 Hz to 4.8 kHz.
Package: 32-lead LFCSP
Interface
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
The device has a very flexible digital filter, including a fast
settling option. Variables such as output data rate and settling
time are dependent on the option selected. For applications that
require all conversions to be settled, the AD7194 includes zero
latency.
APPLICATIONS
The part operates with a power supply from 3 V to 5.25 V. It
PLC/DCS analog input modules
Data acquisition
consumes a current of 4.65 mA, and it is housed in a 32-lead
LFCSP package.
Strain gage transducers
FUNCTIONAL BLOCK DIAGRAM
AV_DD AGND DV_DD DGND
REFIN1(+) REFIN1(–)
AIN1/P3
AIN2/P2
AIN3/P1/REFIN2(+)
AIN4/P0/REFIN2(–)
AIN5
AIN16
AINCOM
AV_DD
AD7194
MUX
PGA
Σ-Δ
ADC
AGND
TEMP
SENSOR
REFERENCE
DETECT
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
CLOCK
CIRCUITRY
Figure 1.
MCLK1 MCLK2
Rev. 0
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