AD9518_2_15 Datasheet, PDF (56/64 Pages) Analog Devices – 6-Output Clock Generator with Integrated 2.2 GHz VCO

AD9518-2
Table 46. LVPECL Channel Dividers
Reg.
Addr.
(Hex) Bits
Name
0x190 [7:4] Divider 0 low cycles
[3:0] Divider 0 high cycles
0x191 7
Divider 0 bypass
6
Divider 0 nosync
5
Divider 0 force high
4
Divider 0 start high
[3:0] Divider 0 phase offset
0x192 1
Divider 0 direct to output
0
Divider 0 DCCOFF
0x193 [7:4] Divider 1 low cycles
[3:0] Divider 1 high cycles
0x194 7
Divider 1 bypass
6
Divider 1 nosync
5
Divider 1 force high
4
Divider 1 start high
[3:0] Divider 1 phase offset
Data Sheet
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that the Divider 0 nosync bit (Bit 6) also be set.
This bit has no effect if the Divider 0 bypass bit (Bit 7) is set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0xB).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0xB).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that the Divider 1 nosync bit (Bit 6) also be set.
This bit has no effect if the Divider 1 bypass bit (Bit 7) is set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Rev. C | Page 56 of 64